| Implementation of N-bit binary multiplication using N-1 bit multiplication based on Nikhilam sutra and Karatsuba principles using complement method MN Angeline, S Valarmathy Circuits and Systems 7 (9), 2332-2338, 2016 | 7 | 2016 |
| Implementation of N-bit Binary multiplication using N-1 bit multiplication based on Nikhilam Sutra principles and bit reduction M Nisha Angeline, S Valarmathy Transylvanian Review 24, 982-992, 2016 | 4 | 2016 |
| Implementation of Hybrid Vedic Multiplier Nikhilam Sutra and Karatsuba algorithm for N-Bit multiplier using successive approximation of N-1 bit multiplier S Nisha Angeline, M & Valarmathy Asian Journal of Information Technology 15 (18), 3508-3604, 2016 | 3* | 2016 |
| P-Match: A Microprocessor Cache Compression Algorithm A Deepa, CN Marimuthu Digital Signal Processing, 467-473, 2011 | 2 | 2011 |
| WITHDRAWN: An improved two-way secure key supervision (tsks) scheme for secure scada NR Kumar, R Nandakumar, RP Meenaakshisundhari, K Siddharthraju, ... Materials Today: Proceedings, 2021 | 1 | 2021 |
| High Throughput LFSR Design for BCH Encoder using Sample Period Reduction Technique for MLC NAND based Flash Memories EKS Nisha Angeline M International Journal of Computer Applications (IJCA) 66 (10), 33-39, 2013 | 1* | 2013 |
| Intelligent Tourniquet System for Emergency AID Using Wireless Network T Venkatesh, MN Angeline, SK Manikandan, S Priyadharshini, K Murugan, ... Soft Computing: Theories and Applications: Proceedings of SoCTA 2020, Volume …, 2021 | | 2021 |
| DESIGN AND ANALYSIS OF VEDIC MULTIPLIER BASED ON YAVADUNAM TAVADUNIKRITYA VARGA YOJAYET SUTRA AM Nisha Angeline. M International Journal of Advance Research in Engineering, Science …, 2018 | | 2018 |
| Security Management for Controlling Theft Using Arduino Uno S Deepika, MN Angeline | | 2017 |
| VLSI Design and FPGA Implementation of N Binary Multiplier Using N-1 Binary Multipliers MNA L. Keerthana International Journal of Science and Research (IJSR) 5 (3), 983-987, 2016 | | 2016 |
| Design and VLSI Implementation of N X N Binary Multiplier Using Successive Approximation of (N-1) X (N-1) Binary Multipliers MNA K. Indumathi International Journal of Science and Research (IJSR) 5 (3), 988-992, 2016 | | 2016 |
| Analysis and design of PHOTON protocol architecture in high speed applications IJSRD - International Journal for Scientific Research & Development 3 (3 …, 2015 | | 2015 |
| Improvement of speed in light weight cryptographic algorithm – Spongent family IJSRD - International Journal for Scientific Research & Development 3 (3 …, 2015 | | 2015 |
| Design of High Speed VLSI Architecture for Quark Family IJSRD - International Journal for Scientific Research & Development 3 (3 …, 2015 | | 2015 |
| VLSI Design of cache compression in microprocessor using burrows wheeler transform algorithm MNA S.Gomathi international Journal of scientific engineering and technology research 3 …, 2014 | | 2014 |
| Analysis and Implementation of Cellular Automata based VLSI Architecture for Error Correcting Codes SK Manikandan, M Nisha Angeline, C Palanisamy International Journal of Computer Applications 49 (17), 30-36, 2012 | | 2012 |
| Nisha Angeline. M Shree Subhatra. K Manikandan. S. K S Valarmathy IEEE Trans. Very Large Scale Integr.(VLSI) Syst 11 (3), 499-510, 2003 | | 2003 |
| Design and implementation of high speed vedic multiplier S Valarmathy Chennai, 0 | | |
| High Throughput LFSR Design for BCH Encoder using Sample Period Reduction Technique for MLC NAND based Flash Memories M SK, S EK International Journal of Computer Applications 975, 8887, 0 | | |
| Area and Timing Analysis of Different PSU’S in P-Match Algorithm for Data Compression in Cache Memories VS Nisha Angeline M International Journal of Computer Applications (IJCA) 65 (22), 5-11, 0 | | |
