| A novel approach for fast and accurate mean error distance computation in approximate adders AS Roy, AS Dhar 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 14 | 2018 |
| Design of content addressable memory architecture using carbon nanotube field effect transistors D Das, AS Roy, H Rahaman Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012 …, 2012 | 13 | 2012 |
| On fast and exact computation of error metrics in approximate LSB adders AS Roy, R Biswas, AS Dhar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (4), 876-889, 2020 | 9 | 2020 |
| SIBAM—sign inclusive broken array multiplier design for error tolerant applications AS Roy, AS Dhar IEEE Transactions on Circuits and Systems II: Express Briefs 67 (11), 2702-2706, 2020 | 5 | 2020 |
| ACBAM-accuracy-configurable sign inclusive broken array Booth multiplier design AS Roy, H Agrawal, AS Dhar IEEE Transactions on Emerging Topics in Computing 10 (4), 2072-2078, 2021 | 4 | 2021 |
| Approximate conditional carry adder for error tolerant applications AS Roy, N Prasad, AS Dhar 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | 3 | 2016 |
| A low-error, memory-based fast binary logarithmic converter B Jana, AS Roy, G Saha, S Banerjee IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2129-2133, 2019 | 2 | 2019 |
| Error Analysis and Design of Approximate Arithmetic Circuits AS Roy IIT Kharagpur, 2023 | | 2023 |
| PERFORMANCE STUDY OF CNT BASED INTERCONNECTS AND DEVICES AS ROY | | 2012 |
| SWCNT Based Interconnect Modeling Using Verilog-AMS H Rahaman, D Das, AS Roy dimensions 6, 22, 0 | | |
Anindya Sundar DharProfessor, Dept. of Electronics and Electrical Communication Engineering, Indian Institute ofVerified email at ece.iitkgp.ernet.in
