Manash Chanda, Ph. D (Engg.)
Manash Chanda, Ph. D (Engg.)
Other namesM Chanda
Associate Professor and Head, Dept. of ECE, Meghnad Saha Institute of Technology, Kolkata 700150
Verified email at - Homepage
Cited by
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Performance assessment of new dual-pocket vertical heterostructure tunnel FET-based biosensor considering steric hindrance issue
A Bhattacharyya, M Chanda, D De
IEEE Transactions on Electron Devices 66 (9), 3988-3993, 2019
Implementation of subthreshold adiabatic logic for ultralow-power application
M Chanda, S Jain, S De, CK Sarkar
IEEE Transactions on very large scale integration (VLSI) systems 23 (12 …, 2015
A review of emerging technologies for IoT-based smart cities
M Whaiduzzaman, A Barros, M Chanda, S Barman, T Sultana, ...
Sensors 22 (23), 9271, 2022
Arrhythmic heartbeat classification using ensemble of random forest and support vector machine algorithm
S Bhattacharyya, S Majumder, P Debnath, M Chanda
IEEE transactions on artificial intelligence 2 (3), 260-268, 2021
Analytical modeling of charge plasma-based optimized nanogap embedded surrounding gate MOSFET for label-free biosensing
R Das, M Chanda, CK Sarkar
IEEE Transactions on Electron Devices 65 (12), 5487-5493, 2018
Analysis of noise-immune dopingless heterojunction bio-TFET considering partial hybridization issue
A Bhattacharyya, M Chanda, D De
IEEE Transactions on Nanotechnology 19, 769-777, 2020
Analysis of partial hybridization and probe positioning on sensitivity of a dielectric modulated junctionless label free biosensor
A Bhattacharyya, M Chanda, D De
IEEE Transactions on Nanotechnology 19, 719-727, 2020
GaAs0. 5Sb0. 5/In0. 53Ga0. 47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement
A Bhattacharyya, M Chanda, D De
Superlattices and Microstructures 142, 106522, 2020
Low power VLSI design: fundamentals
A Sarkar, S De, M Chanda, CK Sarkar
Walter de Gruyter GmbH & Co KG, 2016
Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET
M Chanda, R Das, A Kundu, CK Sarkar
Superlattices and Microstructures 104, 451-460, 2017
Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect
M Chanda, S De, CK Sarkar
Journal of Computational Electronics 14, 262-269, 2015
Split gated silicon nanotube FET for bio‐sensing applications
A Singh, S Chaudhury, M Chanda, CK Sarkar
IET Circuits, Devices & Systems 14 (8), 1289-1294, 2020
Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL)
M Chanda, A Dandapat, H Rahaman
TENCON 2009-2009 IEEE Region 10 Conference, 1-5, 2009
Novel charge plasma based dielectric modulated impact ionization MOSFET as a biosensor for label-free detection
M Chanda, P Dey, S De, CK Sarkar
Superlattices and Microstructures 86, 446-455, 2015
Design and analysis of a logic model for ultra‐low power near threshold adiabatic computing
M Chanda, S Mal, A Mondal, CK Sarkar
IET Circuits, Devices & Systems 12 (4), 439-446, 2018
Analysis of sub-threshold adiabatic logic model using junctionless MOSFET for low power application
S Roy, G Jana, M Chanda
Silicon 14 (3), 903-911, 2022
Analysis of noise margin of CMOS inverter in sub-threshold regime
AS Chakraborty, M Chanda, CK Sarkar
2013 Students Conference on Engineering and Systems (SCES), 1-5, 2013
Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier
M Chanda, S Banerjee, D Saha, S Jain
2013 International Mutli-Conference on Automation, Computing, Communication …, 2013
Sensitivity measurement for bio-TFET considering repulsive steric effects with better accuracy
A Bhattacharyya, D De, M Chanda
IEEE Transactions on Nanotechnology 21, 100-109, 2022
Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications
A Basak, M Chanda, A Sarkar
Microsystem Technologies 27, 3995-4005, 2021
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