Dr. Manash Chanda, Ph. D (Engg.)
Dr. Manash Chanda, Ph. D (Engg.)
Assistant Professor (Senior Grade), MSIT, Kolkata 700150 ; Secretary, IEEE ED Kolkata Chapter
Verified email at ieee.org
TitleCited byYear
Implementation of subthreshold adiabatic logic for ultralow-power application
M Chanda, S Jain, S De, CK Sarkar
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (12 …, 2015
242015
Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL)
M Chanda, A Dandapat, H Rahaman
TENCON 2009-2009 IEEE Region 10 Conference, 1-5, 2009
142009
Low-power sequential circuit using single phase adiabatic dynamic logic
M Chanda, A Dandapat, H Rahaman
Computers and Devices for Communication, 2009. CODEC 2009. 4th International …, 2009
82009
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application
M Chanda, AS Chakraborty, S Nag, R Modak
VLSI Design and Test, 18th International Symposium on, 1-2, 2014
62014
Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier
M Chanda, S Banerjee, D Saha, S Jain
Automation, Computing, Communication, Control and Compressed Sensing (iMac4s …, 2013
62013
Novel charge plasma based dielectric modulated impact ionization MOSFET as a biosensor for label-free detection
M Chanda, P Dey, S De, CK Sarkar
Superlattices and Microstructures 86, 446-455, 2015
52015
Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect
M Chanda, S De, CK Sarkar
Journal of Computational Electronics 14 (1), 262-269, 2015
52015
Comparative Analysis of Adiabatic Compressor Circuits for Ultra-Low power DSP application
M Chanda, P Sil, R Mitra, A Dandapat, H Rahaman
Advances in Recent Technologies in Communication and Computing (ARTCom …, 2010
42010
Analysis of noise margin of CMOS inverter in sub-threshold regime
AS Chakraborty, M Chanda, CK Sarkar
Engineering and Systems (SCES), 2013 Students Conference on, 1-5, 2013
32013
Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET
M Chanda, R Das, A Kundu, CK Sarkar
Superlattices and Microstructures 104, 451-460, 2017
22017
Low Power VLSI Design: Fundamentals
A Sarkar, S De, M Chanda, CK Sarkar
Walter de Gruyter GmbH & Co KG, 2016
22016
Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application
M Chanda, D Sinha, J Basak, T Ganguli, CK Sarkar
Communication and Signal Processing (ICCSP), 2016 International Conference …, 2016
22016
Design and implementation of adiabatic multiplier in sub-threshold regime for ultra low power application
M Chanda, J Basak, D Sinha, T Ganguli, CK Sarkar
Communication and Signal Processing (ICCSP), 2016 International Conference …, 2016
22016
Design and analysis of tree-multiplier using single-clocked energy efficient adiabatic Logic
M Chanda, S Kundu, I Adak, A Dandapat, H Rahaman
Students' Technology Symposium (TechSym), 2011 IEEE, 232-236, 2011
22011
Analytical Modeling of Charge Plasma-Based Optimized Nanogap Embedded Surrounding Gate MOSFET for Label-Free Biosensing
R Das, M Chanda, CK Sarkar
IEEE Transactions on Electron Devices 65 (12), 5487-5493, 2018
12018
Design and analysis of adiabatic logic in sub-threshold regime for ultra low power application
M Chanda, D Sinha, J Basak, T Ganguli, CK Sarkar
Emerging Devices and Smart Systems (ICEDSS), Conference on, 42-47, 2016
12016
Doping-less double gate impact ionization MOSFET for high switching application
M Chanda, P Dey, A Sarkar, CK Sarkar
Devices, Circuits and Systems (ICDCS), 2016 3rd International Conference on …, 2016
12016
Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application
M Chanda, AS Chakraborty, CK Sarkar
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2016
12016
Modeling of Subthreshold Surface Potential for Short Channel Double Gate Dual Material Double Halo MOSFET.
D Das, S De, M Chanda, C Kumar Sarkar
IUP Journal of Electrical & Electronics Engineering 7 (4), 2014
12014
Modeling of parameters for nano‐scale surrounding‐gate MOSFET considering quantum mechanical effect
M Chanda, S De, CK Sarkar
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2014
12014
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Articles 1–20