| Hardware optimization of complex multiplication scheme for DSP application M Hemnani, S Palekar, P Dixit, P Joshi 2015 International Conference on Computer, Communication and Control (IC4), 1-4, 2015 | 16 | 2015 |
| Power-Area Efficient Computing Technique for Approximate Multiplier with Carry Prediction PU Joshi, D Khushlani, R Khobragade 2023 11th International Conference on Emerging Trends in Engineering …, 2023 | 4 | 2023 |
| Self‐compensation scheme for truncation error in fixed width multipliers PU Joshi, RB Deshmukh, V Gudur IET Circuits, Devices & Systems 12 (1), 55-62, 2018 | 3 | 2018 |
| Low Power Complex Multiplication using Pre-computation Technique for FFT Algorithm in Wearable ECG Gadgets PU Joshi, VS Lande Bioscience Biotechnology Research Communications 13 (14), 2020 | 2 | 2020 |
| A novel combined approach of constant correction and variable correction method to minimize the mean square error and compensation hardware for fixed width multiplier design P Joshi, RB Deshmukh, K Pandey, S Admane 2015 IEEE International Conference on Electronics, Computing and …, 2015 | 2 | 2015 |
| An Insight into EDGE-Based Solutions for Augmented Reality P Joshi, S Jain, S Vanjani Proceedings of Fourth International Conference on Communication, Computing …, 2023 | 1 | 2023 |
| Covid Security System Using IOT Monitoring System C Mohadikar, R Najbile, V Kaushik, Y Konghe, D Khushalani, P Joshi The International Journal of Next-Generation Computing (IJNGC) 13 (5), 2022 | 1 | 2022 |
| A Generalized Power Reduction Technique for Truncated Multiplier via Latching the Data Inputs and Error Compensating Carry PU Joshi, RB Deshmukh Iranian Journal of Science and Technology, Transactions of Electrical …, 2024 | | 2024 |
| Edge Computing: Attributes, Applications, and Future Trends PU Joshi, D Khushalani, T Chhaware, Y Jain, S Bharati International Conference on Communication, Electronics and Digital …, 2023 | | 2023 |
| Design and Analysis of Multipliers for DNN application using approximate 4: 2 Compressors. H Gillurkar, P Dwaramwar, S Anjankar, P Joshi International Journal of Next-Generation Computing 13 (5), 2022 | | 2022 |
| Performance Improvement of Mont gomery Multiplier Architecture U sing Pre - Computation and Unfolding Technique PJ Prafulani Gajbhiye HELIX -The Scientific Explorer 8 (6), 4433-4440, 2018 | | 2018 |
| Data dependent spurious power reduction for fixed width multiplier B Navlani, P Joshi, RB Deshmukh 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-2, 2016 | | 2016 |
| Hardware Optimization of Complex Multipleir Scheme for DSP Application SP Pankaj Joshi, Monika Hemnani, Preeti Dixit ICCCC Indore, 2015 | | 2015 |
| Power Optimization of FIR Filter SA Pankaj Joshi, Saiyma Raza TechEd-2015 on Science Technology and Mathematics Education-Trends and …, 2015 | | 2015 |
| Single Precision Floating Point FFT Design in Fully Combinational Circuits PJ Ujwal Ghate Electronics Computer Technology (ICECT 2012) 6-7 April 2012, 2012 | | 2012 |
| Proposed IDWT Architecture Based on MATLAB Results PK Pankaj Joshi, V S Lande Journal of Computer Application, 2012 | | 2012 |
| High speed pipelined Implementation of Radix -2 DIT Algorithm PJ Shrikant Chamlate Emerging Trends in Signal Processing and VLSI Design 11-12 June 2010, 2010 | | 2010 |
| Implementation of FFT on FPGA SC Pankaj Joshi Universal Trends in Signal Processing, Advanced Computing and VLSI …, 2009 | | 2009 |
| DWT System Implementation in Verilog PA Pankaj Joshi, M B Damle Emerging Techniques in Computing Electronics, Embedded Systems & VLSI Design …, 2008 | | 2008 |
| Proposed IDWT architecture based on MATLAB results P Kamble, P Joshi, V Lande image 1, 2, 0 | | |
