Suivre
Chittaranjan Mandal
Chittaranjan Mandal
Dept of Computer Sc & Engg, IIT Kharagpur
Adresse e-mail validée de iitkgp.ac.in - Page d'accueil
Titre
Citée par
Citée par
Année
Automatic detection of human fall in video
V Vishwakarma, C Mandal, S Sural
Pattern Recognition and Machine Intelligence: Second International …, 2007
1862007
Performance comparison of AODV/DSR on-demand routing protocols for ad hoc networks in constrained situation
R Misra, C Mandal
Personal Wireless Communications, 2005. ICPWC 2005. 2005 IEEE International …, 2005
1772005
Minimum connected dominating set using a collaborative cover heuristic for ad hoc sensor networks
R Misra, C Mandal
IEEE Transactions on parallel and distributed systems 21 (3), 292-302, 2009
1232009
Ant-aggregation: ant colony algorithm for optimal data aggregation in wireless sensor networks
R Misra, C Mandal
2006 IFIP International Conference on Wireless and Optical Communications …, 2006
1042006
An equivalence-checking method for scheduling verification in high-level synthesis
C Karfa, D Sarkar, C Mandal, P Kumar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
792008
Rotation of CDS via connected domatic partition in ad hoc sensor networks
R Misra, C Mandal
Mobile Computing, IEEE Transactions on 8 (4), 488-499, 2009
762009
Verification of code motion techniques using value propagation
K Banerjee, C Karfa, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
702014
GABIND: A GA Approach to Allocation and Binding for the High-Level Synthesis of Data Paths
C Mandal, PP Chakrabarti, S Ghose
IEEE Transactions on Very Large Scale Integration Systems 8 (6), 747-749, 2000
702000
Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set
JP Mohanty, C Mandal, CMP Reade
Ad Hoc Networks 42, 61-73, 2016
572016
Formal verification of code motion techniques using data-flow-driven equivalence checking
C Karfa, C Mandal, D Sarkar
ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3 …, 2012
542012
A formal verification method of scheduling in high-level synthesis
C Karfa, C Mandal, D Sarkar, SR Pentakota, CMP Reade
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-78, 2006
532006
Complexity of fragmentable object bin packing and an application
C Mandal, PP Chakrabarti, S Ghose
Computers & Mathematics with Applications 35 (11), 91-97, 1998
521998
Distributed Construction of Minimum Connected Dominating Set in Wireless Sensor Network Using Two-Hop Information
JP Mohanty, C Mandal, CMP Reade
Computer Networks, 2017
502017
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
C Karfa, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
41*2010
Nano-scale CMOS analog circuits: models and CAD techniques for high-level design
S Pandit, C Mandal, A Patra
CRC Press, 2018
36*2018
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviours
C Karfa, K Banerjee, D Sarkar, C Mandal
IEEE Transactions on CAD 32 (11), 1787--1800, 2013
35*2013
An Improved Greedy Construction of Minimum Connected Dominating Sets in Wireless Networks
A Das, M Aasawat, C Mandal, CMP Reade
2011 IEEE Wireless Communications and Networking Conference, 790-795, 2011
352011
CURE: Consistent Update with Redundancy Reduction in SDN
I Maity, A Mondal, S Misra, C Mandal
IEEE Transactions on Communications, 2018
332018
Efficient clusterhead rotation via domatic partition in self‐organizing sensor networks
R Misra, C Mandal
Wireless Communications and Mobile Computing 9 (8), 1040-1058, 2009
33*2009
A design space exploration scheme for data-path synthesis
C Mandal, PP Chakrabarti, S Ghose
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 331-338, 1999
31*1999
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