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Prof.  Rishu Chaujar
Prof. Rishu Chaujar
Department of Applied Physics, Delhi Technological University
Verified email at dtu.ac.in
Title
Cited by
Cited by
Year
Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability
J Madan, R Chaujar
IEEE Transactions on Device and Materials Reliability 16 (2), 227-234, 2016
1502016
Numerical Simulation of N+Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature
J Madan, R Chaujar
IEEE Transactions on Electron Devices 64 (4), 1482-1488, 2017
772017
Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance
J Madan, R Chaujar
Superlattices and Microstructures 102, 17-26, 2017
612017
Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor
SP Kumar, A Agrawal, R Chaujar, RS Gupta, M Gupta
Microelectronics Reliability 51 (3), 587-596, 2011
602011
Numerical simulations: Toward the design of 27.6% efficient four-terminal semi-transparent perovskite/SiC passivated rear contact silicon tandem solar cell
R Pandey, R Chaujar
Superlattices and Microstructures 100, 656-666, 2016
542016
Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN/GaN HEMT
SP Kumar, A Agrawal, R Chaujar, M Gupta, RS Gupta
Superlattices and Microstructures 44 (1), 37-53, 2008
442008
TCAD RF performance investigation of transparent gate recessed channel MOSFET
A Kumar, N Gupta, R Chaujar
Microelectronics Journal 49, 36-42, 2016
422016
Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature
A Kumar, MM Tripathi, R Chaujar
IEEE Transactions on Electron Devices 65 (3), 860-866, 2018
412018
Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour
A Kumar, N Gupta, R Chaujar
Microsystem technologies 22 (11), 2665-2671, 2016
412016
Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET
N Gupta, R Chaujar
Superlattices and Microstructures 97, 630-641, 2016
402016
Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications
A Kumar, MM Tripathi, R Chaujar
Superlattices and Microstructures 116, 171-180, 2018
372018
TCAD assessment of gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET and its multilayered gate architecture—part I: hot-carrier-reliability evaluation
R Chaujar, R Kaur, M Saxena, M Gupta, RS Gupta
IEEE transactions on electron devices 55 (10), 2602-2613, 2008
372008
Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation
SP Kumar, A Agrawal, R Chaujar, S Kabra, M Gupta, RS Gupta
Microelectronics Journal 38 (10-11), 1013-1020, 2007
372007
Temperature associated reliability issues of heterogeneous gate dielectric—Gate all around—Tunnel FET
J Madan, R Chaujar
IEEE Transactions on nanotechnology 17 (1), 41-48, 2017
362017
Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET
N Gupta, A Kumar, R Chaujar
Journal of Computational Electronics 14 (3), 798-810, 2015
352015
Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior
J Madan, R Chaujar
Applied Physics A 122 (11), 1-9, 2016
342016
Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications
A Kumar, MM Tripathi, R Chaujar
Microsystem Technologies 23 (12), 5867-5874, 2017
332017
Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications
J Madan, RS Gupta, R Chaujar
Microsystem Technologies 23 (9), 4091-4098, 2017
312017
Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications
J Madan, RS Gupta, R Chaujar
Microsystem Technologies 23 (9), 4081-4090, 2017
302017
Numerical simulations: Toward the design of 18.6% efficient and stable perovskite solar cell using reduced cerium oxide based ETL
R Pandey, AP Saini, R Chaujar
Vacuum 159, 173-181, 2019
292019
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