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Narasimhulu Thoti
Narasimhulu Thoti
Postdoctoral Researcher, University of Oulu
Verified email at oulu.fi - Homepage
Title
Cited by
Cited by
Year
Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers
SR Kola, N Thoti
2020 International Conference on Simulation of Semiconductor Processes and …, 2020
182020
RF performance enhancement in multi-fin TFETs by scaling inter fin separation
N Thoti, B Lakshmi
Materials Science in Semiconductor Processing 71, 304-309, 2017
182017
Influence of Fringing-Field on DC/AC Characteristics of Si₁₋Ge Based Multi-Channel Tunnel FETs
N Thoti, Y Li
IEEE Access 8, 208658-208668, 2020
172020
Effects of spacer and single-charge trap on voltage transfer characteristics of gate-all-around silicon nanowire CMOS devices and circuits
SR Kola, Y Li, N Thoti
2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO), 217-220, 2020
172020
Significance of work function fluctuations in SiGe/Si hetero-nanosheet tunnel-FET at sub-3 nm nodes
N Thoti, Y Li, WL Sung
IEEE Transactions on Electron Devices 69 (1), 434-438, 2021
162021
Optimal inter-gate separation and overlapped source of multi-channel line tunnel FETs
N Thoti, Y Li, SR Kola, S Samukawa
IEEE Open Journal of Nanotechnology 1, 38-46, 2020
162020
Random telegraph noise in gate-all-around silicon nanowire MOSFETs induced by a single charge trap or random interface traps
SR Kola, Y Li, N Thoti
Journal of Computational Electronics 19, 253-262, 2020
162020
Effects of a dual spacer on electrical characteristics and random telegraph noise of gate-all-around silicon nanowire p-type metal–oxide–semiconductor field-effect transistors
SR Kola, Y Li, N Thoti
Japanese Journal of Applied Physics 59 (SG), SGGA02, 2020
122020
Design of GAA nanosheet ferroelectric area tunneling FET and its significance with DC/RF characteristics including linearity analyses
N Thoti, Y Li
Nanoscale Research Letters 17 (1), 53, 2022
102022
Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification
N Thoti, Y Li
Nanotechnology 33 (5), 055201, 2021
92021
Promised Design of Energy-Efficient Negative-Capacitance Vertical Tunneling FET
N Thoti, Y Li
ECS Journal of Solid State Science and Technology 10 (7), 075002, 2021
92021
p-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric
N Thoti, Y Li
Japanese Journal of Applied Physics 60 (5), 054001-1-5, 2021
72021
High-Performance Metal-Ferroeletric-Semiconductor Nanosheet Line Tunneling Field Effect Transistors with Strained SiGe
N Thoti, Y Li, SR Kola, S Samukawa
2020 International Conference on Simulation of Semiconductor Processes and …, 2020
72020
New proficient ferroelectric nanosheet line tunneling FETs with strained SiGe through scaled n-epitaxial layer
N Thoti, Y Li, SR Kola, S Samukawa
2020 IEEE 20th International Conference on Nanotechnology (IEEE-NANO), 319-322, 2020
72020
Implementation of video steganography using hash function in LSB technique
S Chitra, N Thoti
International Journal of Engineering Research & Technology (IJERT) 2 (11 …, 2013
6*2013
Machine learning approach to predicting tunnel field-effect transistors
C Akbar, N Thoti, Y Li
2021 International Symposium on VLSI Technology, Systems and Applications …, 2021
42021
Scaling limitations of line TFETs at sub-8-nm technology node
N Thoti, Y Li, SR Kola
2020 International Symposium on VLSI Technology, Systems and Applications …, 2020
42020
Device-simulation-based machine learning technique for the characteristic of line tunnel field-effect transistors
C Akbar, Y Li, N Thoti
IEEE Access 10, 53098-53107, 2022
22022
Investigation of optimized Si1-xGex 3D-fin-TFET by varying the fin height
N Thoti, R Haritha, N Madineni
2018 International Conference on Recent Trends in Electrical, Control and …, 2018
22018
A novel design of ferroelectric nanowire tunnel field effect transistors
N Thoti, Y Li
2021 International Symposium on VLSI Technology, Systems and Applications …, 2021
12021
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