| A normal I/O order radix-2 FFT architecture to process twin data streams for MIMO AX Glittas, M Sellathurai, G Lakshminarayanan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2016 | 40 | 2016 |
| A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition AX Glittas, L Gopalakrishnan Integration 76, 69-75, 2021 | 16 | 2021 |
| Pipelined FFT architectures for real-time signal processing and wireless communication applications AX Glittas, G Lakshminarayanan 18th International Symposium on VLSI Design and Test, 1-2, 2014 | 9 | 2014 |
| Reconfigurable 2, 3 and 5‐point DFT processing element for SDF FFT architecture using fast cyclic convolution algorithm AX Glittas, M Sellathurai, G Lakshminarayanan Electronics Letters 56 (12), 592-594, 2020 | 3 | 2020 |
| A power-efficient variable-length prime factor MDC FFT architecture for high-speed wireless communication applications AXGX Chelliah, BSPS Robinson, M Sellathurai, L Gopalakrishnan AEU-International Journal of Electronics and Communications 120, 153194, 2020 | 2 | 2020 |
| Two‐parallel pipelined fast Fourier transform processors for real‐valued signals A Xavier Glittas, M Sellathurai, G Lakshminarayanan IET Circuits, Devices & Systems 10 (4), 330-336, 2016 | 2 | 2016 |
| A normal I/O order optimized dual-mode pipelined FFT architecture for processing real-valued signals and complex-valued signals AXGX Chelliah AEU-International Journal of Electronics and Communications 170, 154782, 2023 | | 2023 |
| Data scheduling register tree for radix-2 FFT architecture G Lakshminarayanan, AX Glittas, M Sellathurai US Patent 11,531,497, 2022 | | 2022 |
Mathini Sellathurai, IEEE FellowHeriot-Watt University, EdinburghVerified email at ieee.org
