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Yakir Vizel
Yakir Vizel
Verified email at cs.technion.ac.il - Homepage
Title
Cited by
Cited by
Year
Boolean satisfiability solvers and their applications in model checking
Y Vizel, G Weissenbacher, S Malik
Proceedings of the IEEE 103 (11), 2021-2035, 2015
1192015
Interpolation-sequence based model checking
Y Vizel, O Grumberg
2009 Formal Methods in Computer-Aided Design, 1-8, 2009
712009
Interpolating property directed reachability
Y Vizel, A Gurfinkel
Computer Aided Verification: 26th International Conference, CAV 2014, Held …, 2014
482014
Lazy abstraction and sat-based reachability in hardware model checking
Y Vizel, O Grumberg, S Shoham
2012 Formal Methods in Computer-Aided Design (FMCAD), 173-181, 2012
462012
Instruction-level abstraction (ila) a uniform specification for system-on-chip (soc) verification
BY Huang, H Zhang, P Subramanyan, Y Vizel, A Gupta, S Malik
ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (1 …, 2018
432018
Property directed self composition
R Shemer, A Gurfinkel, S Shoham, Y Vizel
Computer Aided Verification: 31st International Conference, CAV 2019, New …, 2019
392019
Quantifiers on demand
A Gurfinkel, S Shoham, Y Vizel
Automated Technology for Verification and Analysis: 16th International …, 2018
392018
Template-based synthesis of instruction-level abstractions for SoC verification
P Subramanyan, Y Vizel, S Ray, S Malik
2015 Formal Methods in Computer-Aided Design (FMCAD), 160-167, 2015
372015
Intertwined forward-backward reachability analysis using interpolants
Y Vizel, O Grumberg, S Shoham
Tools and Algorithms for the Construction and Analysis of Systems: 19th …, 2013
242013
Lazy self-composition for security verification
W Yang, Y Vizel, P Subramanyan, A Gupta, S Malik
Computer Aided Verification: 30th International Conference, CAV 2018, Held …, 2018
222018
Efficient generation of small interpolants in CNF
Y Vizel, A Nadel, V Ryvchin
Formal Methods in System Design 47, 51-74, 2015
222015
Template-based parameterized synthesis of uniform instruction-level abstractions for SoC verification
P Subramanyan, BY Huang, Y Vizel, A Gupta, S Malik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
182017
Druping for interpolates
A Gurfinkel, Y Vizel
2014 Formal Methods in Computer-Aided Design (FMCAD), 99-106, 2014
182014
Interpolating strong induction
HG Vediramana Krishnan, Y Vizel, V Ganesh, A Gurfinkel
Computer Aided Verification: 31st International Conference, CAV 2019, New …, 2019
142019
Fast interpolating BMC
Y Vizel, A Gurfinkel, S Malik
Computer Aided Verification: 27th International Conference, CAV 2015, San …, 2015
132015
IC3-flipping the E in ICE
Y Vizel, A Gurfinkel, S Shoham, S Malik
Verification, Model Checking, and Abstract Interpretation: 18th …, 2017
102017
Solving linear arithmetic with SAT-based model checking
Y Vizel, A Nadel, S Malik
2017 Formal Methods in Computer Aided Design (FMCAD), 47-54, 2017
92017
Error-tolerant processors: Formal specification and verification
A Golnari, Y Vizel, S Malik
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 286-293, 2015
82015
Deeper bound in BMC by combining constant propagation and abstraction
R Armoni, L Fix, R Fraer, T Heyman, M Vardi, Y Vizel, Y Zbar
2007 Asia and South Pacific Design Automation Conference, 304-309, 2007
72007
Efficient information-flow verification under speculative execution
R Bloem, S Jacobs, Y Vizel
Automated Technology for Verification and Analysis: 17th International …, 2019
52019
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