Saurabh Kumar Nema

Senior Verification Engineer, Intel Technology, Bangalore

Verified email at iitr.ac.in


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Improved Underlap FinFET with Asymmetric Spacer Permittivities SK Nema, M SaiKiran, P Singh, A Pandey, SK Manhas, AK Saxena, ... Physics of Semiconductor Devices, 267-268, 2013		2013
Nano-scale Finfets: Device and Circuits Design Methodology Saurabh K. Nema Indian Institute of Technology Roorkee, 2010		2010
A Novel Scaling Strategy for Underlap FinFETs AB Saurabh Nema, Mayank Srivastava, Angada B. Sachid, Ashok K. Saxena International Conference on Communication, Computers and Devices, Kharagpur,, 2010		2010

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