| Design and implementation of Novel 32-bit MAC unit for DSP applications HM Rakesh, GS Sunitha 2020 International Conference for Emerging Technology (INCET), 1-6, 2020 | 13 | 2020 |
| Performance Comparison of conventional multiplier with vedic multiplier using ISE simulator GS Sunitha, HM Rakesh International Journal of Engineering and Manufacturing Science 8 (1), 95-103, 2018 | 5 | 2018 |
| Efficient High Performance Successive Cancelation Decoder for Polar Code KM Prakash, GS Sunitha 2018 3rd IEEE International Conference on Recent Trends in Electronics …, 2018 | 2 | 2018 |
| Design and Implementation of Adder Architectures and Analysis of Performance Metrics DGS Sunitha, HM Rakesh International Journal of Electronics and Communication Engineering and …, 2017 | 1 | 2017 |
| Complexity reduction scheme in encoding and decoding for polar codes KM Prakash, GS Sunitha 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 1 | 2016 |
| Design of Four Port Router for Network on Chip DGSS Savithri G R International Journal Of Engineering Research & Technology (IJERT) 10 (11), 2022 | | 2022 |
| Design of Decimation Filters for Wireless Local Area Network Applications SON Kantharaj S P,G. S. Sunitha ,G. H. Leela International Journal of Electronics and Communications System 2 (1), 9-13, 2022 | | 2022 |
| Design and Implementation of Efficient 4x4 Vedic Multiplier for DSP Applications HM Rakesh, GS SUNITHA Design Engineering, 8694-8703, 2021 | | 2021 |
| Design and Verification of CMOS LDO Regulator SNS Dr. G S Sunitha, Viresh Banakar, Shravya N 2nd international conference on Emerging trends in Science, Engineering And …, 2021 | | 2021 |
| A Survey on Architectures of MAC units for DSP Applications HM Rakesh, GS Sunitha European Journal of Advances in Engineering and Technology 6 (4), 36-39, 2019 | | 2019 |
| A Modified-SCD for Optimize Performance Rate at Polar Code KM Prakash, GS Sunitha International Journal of Green Computing (IJGC) 10 (1), 1-21, 2019 | | 2019 |
| Comparative analysis of 16 x 16 bit Vedic and Booth multipliers DGSS Rakesh H.M World Journal of Engineering Research and Technology (WJERT) 3 (1), pp.305-313, 2018 | | 2018 |
| Design and Implementation of Vedic and Booth multiplier on spartan 3 DGSS Rakesh H.M International Journal of VLSI Design, Microelectronics and Embedded System 2 …, 2017 | | 2017 |
| Non-recursive complexity reduction encoding scheme for performance enhancement of polar codes DSGS Prakash K M International Journal of Engineering and Technology (IJET) 9 (1), 2017 | | 2017 |
| Performance Metrics of ATM & IP Network for Multiple Profiles with 99%Background Utilization of Link S G S, S chandramohan International Journal of Electronics Communication and Computer Engineering …, 2013 | | 2013 |
| “Performance Comparison of ATM and IP Network for Multiple Profiles using OPNET Simulator” Sunitha G S, Suresh Chandra Mohan International Journal on Communications Antenna and Propagation( IRECAP) 1 …, 2011 | | 2011 |
| Design of Finite Impulse Response Filters for Sampling Rate Conversion SP Kantharaj, GS Sunitha, KC Shilpa, MB Srikanth | | |
| Design of FIR filters for Smapling Rate Conversion KSPDGS Sunitha | | |
