| A Novel low power and high speed Wallace tree multiplier for RISC processor C Vinoth, VSK Bhaaskaran, B Brindha, S Sakthikumaran, V Kavinilavu, ... 3rd International Conference on Electronics Computer Technology (ICECT), 2011, 5, 2011 | 60 | 2011 |
| 16-Bit RISC processor design for convolution application S Sakthikumaran, S Salivahanan, VSK Bhaaskaran 2011 International Conference on Recent Trends in Information Technology …, 2011 | 51 | 2011 |
| Energy recovery performance of quasi-adiabatic circuits using lower technology nodes VSK Bhaaskaran India international conference on power electronics 2010 (IICPE2010), 1-7, 2011 | 38 | 2011 |
| Differential cascode adiabatic logic structure for low power VS Bhaaskaran, JP Raina Journal of Low Power Electronics 4 (2), 178-190, 2008 | 38 | 2008 |
| A very fast and low power carry select adder circuit S Sakthikumaran, S Salivahanan, VSK Bhaaskaran, V Kavinilavu, ... 2011 3rd International Conference on Electronics Computer Technology 1, 273-276, 2011 | 35 | 2011 |
| Implementation of Convolutional encoder and Viterbi decoder using Verilog HDL V Kavinilavu, S Salivahanan, VSK Bhaaskaran, S Sakthikumaran, ... 2011 3rd International Conference on Electronics Computer Technology 1, 297-300, 2011 | 34 | 2011 |
| Semi-custom design of adiabatic adder circuits VSK Bhaaskaran, S Salivahanan, DS Emmanuel 19th International Conference on VLSI Design Held Jointly with 5th …, 2006 | 29 | 2006 |
| Two-phase sinusoidal power-clocked quasi-adiabatic logic circuits VS Kanchana Bhaaskaran, JP Raina Journal of Circuits, Systems, and Computers 19 (02), 335-347, 2010 | 26 | 2010 |
| Lightweight S-box architecture for secure internet of things A Prathiba, VSK Bhaaskaran Information 9 (1), 13, 2018 | 24 | 2018 |
| Area efficient hybrid parallel prefix adders N Poornima, VSK Bhaaskaran Procedia Materials Science 10, 371-380, 2015 | 23 | 2015 |
| Pre-resolve and sense adiabatic logic for 100 KHz to 500 MHz frequency classes VS Kanchana Bhaaskaran, JP Raina Journal of Circuits, Systems, and Computers 21 (05), 1250045, 2012 | 22 | 2012 |
| Evaluation of the conventional vs. ancient computation methodology for energy efficient arithmetic architecture V Jayaprakasan, S Vijayakumar, VSK Bhaaskaran 2011 International Conference on Process Automation, Control and Computing, 1-4, 2011 | 21 | 2011 |
| Low power vedic multiplier using energy recovery logic H Sangani, TM Modi, VSK Bhaaskaran 2014 International Conference on Advances in Computing, Communications and …, 2014 | 20 | 2014 |
| Linear Integrated Circuits S Salivahanan, VSK Bhaaskaran McGraw-Hill Education, 2008 | 18 | 2008 |
| High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits A Anita Angeline, VS Kanchana Bhaaskaran ETRI Journal 41 (3), 383-395, 2019 | 17 | 2019 |
| Optimization of power and energy in FinFET based SRAM cell using adiabatic logic S Patil, VSK Bhaaskaran 2017 International Conference on Nextgen Electronic Technologies: Silicon to …, 2017 | 17 | 2017 |
| Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit AA Angeline, VS Kanchana Bhaaskaran IET Circuits, Devices & Systems 13 (8), 1134-1141, 2019 | 16 | 2019 |
| Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems A Prathiba, VSK Bhaaskaran Integration 69, 266-278, 2019 | 15 | 2019 |
| Low power divider using vedic mathematics DR Kishor, VSK Bhaaskaran 2014 International Conference on Advances in Computing, Communications and …, 2014 | 13 | 2014 |
| Design and implementation of an efficient multiplier using vedic mathematics and charge recovery logic BR Appasaheb, VS Kanchana Bhaaskaran Proceedings of International Conference on VLSI, Communication, Advanced …, 2013 | 13 | 2013 |
Anita Angeline AVITVerified email at vit.ac.in
