| Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance A Kundu, A Dasgupta, R Das, S Chakraborty, A Dutta, CK Sarkar Superlattices and Microstructures 94, 60-73, 2016 | 41 | 2016 |
| Analytical Modeling of Charge Plasma-Based Optimized Nanogap Embedded Surrounding Gate MOSFET for Label-Free Biosensing R Das, M Chanda, CK Sarkar IEEE Transactions on Electron Devices 65 (12), 5487-5493, 2018 | 35 | 2018 |
| Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET M Chanda, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 104, 451-460, 2017 | 27 | 2017 |
| Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture R Das, S Chakraborty, A Dasgupta, A Dutta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 386-396, 2016 | 14 | 2016 |
| Comparisons between dual and tri material gate on a 32 nm double gate MOSFET A Dasgupta, R Das, S Chakraborty, A Dutta, A Kundu, CK Sarkar Nano 11 (10), 1650117, 2016 | 11 | 2016 |
| Analytical modeling of sensitivity parameters influenced by practically feasible arrangement of bio-molecules in dielectric modulated FET biosensor R Das, A Chattopadhyay, M Chanda, CK Sarkar, C Bose Silicon 14 (15), 9417-9430, 2022 | 8 | 2022 |
| Impact of lateral straggle on the analog/RF performance of asymmetric gate stack double gate MOSFET GS Sivaram, S Chakraborty, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 477-488, 2016 | 8 | 2016 |
| A linearity based comparison between symmetric and asymmetric lateral diffusion for a 22 nm Underlapped DG-MOSFET A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar Superlattices and Microstructures 107, 69-82, 2017 | 6 | 2017 |
| An optimisation based study of underlap architecture of sub 16 nm double gate MOSFET for enhanced analog performance R Das, P Pandit, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar Materials Focus 6 (3), 305-309, 2017 | 6 | 2017 |
| Effect of spacer dielectric engineering on asymmetric source underlapped double gate MOSFET using gate stack A Chattopadhyay, A Dasgupta, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 101, 87-95, 2017 | 5 | 2017 |
| Effect of channel engineering on analog/RF performance of underlapped gatestack DG-MOSFET in Sub-20nm regime A Chattopadhyay, R Das, A Dasgupta, A Kundu, CK Sarkar 2017 Devices for Integrated Circuit (DevIC), 299-302, 2017 | 4 | 2017 |
| An RF Based Optimization of Underlap of Sub 16 nm Double Gate MOSFET P Pandit, R Das, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar Advances in Industrial Engineering and Management 6 (1), 6-10, 2017 | 3 | 2017 |
| A comparative study of analog/RF performance: symmetric and asymmetric underlap gate stack DG-MOSFETs A Dasgupta, R Das, A Dutta, A Kundu, CK Sarkar 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 3 | 2016 |
| Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET R Ray, R Das, M Chanda Microsystem Technologies 27, 4041-4049, 2021 | 2 | 2021 |
| Reliability analysis through linearity and harmonic distortion of a dual-material-gate asymmetric underlapped DGMOSFET R Das, A Dasgupta, A Kundu Microelectronics Reliability 92, 106-113, 2019 | 2 | 2019 |
| Impact of asymmetric dual-k spacer in the underlap regions of sub 20 nm NMOSFET with gate stack S Chakraborty, A Dasgupta, R Das, A Kundu, CK Sarkar Superlattices and Microstructures 98, 448-457, 2016 | 2 | 2016 |
| Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach S Chakraborty, A Dasgupta, R Das, M Kar, A Kundu, CK Sarkar Journal of Semiconductors 38 (12), 124001-1 to 124001-5, 2017 | 1 | 2017 |
| An Extensive Study on Different Underlap Architectures for Improved Analog/RF Performance of 32 nm DG-MOSFET A Singh, A Dasgupta, R Das, A Kundu, S Chaudhury | | |
Atanu KunduHeritage Institute of TechnologyVerified email at heritageit.edu
