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Satish S Bhairannawar
Satish S Bhairannawar
Dean & Professor, Electronics and Communication,SDMCET, VTU
Verified email at sdmcet.ac.in
Title
Cited by
Cited by
Year
Color image enhancement using Laplacian filter and contrast limited adaptive histogram equalization
S Bhairannawar, A Patil, A Janmane, M Huilgol
IEEE, Power and Advanced Computing Technologies (i-PACT), 2017 Innovations …, 2017
202017
Design and Implementation of High Speed Background Subtraction Algorithm for Moving Object Detection
SR Hanchinamani, S Sarkar, SS Bhairannawar
6th International Conference On Advances In Computing & Communications …, 2016
182016
Implementation of fingerprint based biometric system using optimized 5/3 DWT architecture and modified CORDIC based FFT
SS Bhairannawar, S Sarkar, KB Raja, KR Venugopal
Circuits, Systems, and Signal Processing, Springer 37 (1), 342-366, 2018
142018
Efficient Medical Image Enhancement Technique Using Transform HSV Space and Adaptive Histogram Equalization
SS Bhairannawar
Soft Computing Based Medical Image Analysis, Elsevier, 51-60, 2018
132018
An efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT
SS Bhairannawar, S Sarkar, KB Raja, KR Venugopal
2015 IEEE International Conference on Signal Processing, Informatics …, 2015
122015
FPGA IMPLEMENTATION OF MOVING OBJECT AND FACE DETECTION USING ADAPTIVE THRESHOLD
Sateesh Kumar H.C., Sayantam Sarkar, Satish S Bhairannawar, Raja K.B ...
International Journal of VLSI design & Communication Systems (VLSICS) 6 (5), 20, 2015
10*2015
A novel FPGA based reconfigurable architecture for image color space conversion
MC Hanumantharaju, GR Vishalakshi, S Halvi, SB Satish
International Conference on Computing and Communication Systems, 292-301, 2011
102011
Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
S Sarkar, SS Bhairannawar
Multidimensional Systems and Signal Processing 32 (2), 821-844, 2021
72021
FPGA implementation of face recognition system using efficient 5/3 2D-lifting scheme
SS Bhairannawar, R Kumar, V Mirji, PS Sindhu
IEEE, VLSI Systems, Architectures, Technology and Applications (VLSI-SATA …, 2016
72016
FPGA Implementation of Optimized Karhunen–Loeve Transform for Image Processing Applications
SS Bhairannawar, S Sarkar, KB Raja
Journal of Real-Time Image Processing, Springer, 1-14, 2018
52018
AN EFFICIENT RECONFIGURABLE ARCHITECTURE FOR FINGERPRINT RECOGNITION
SS Bhairannawar, KB Raja, KR Venugopal
VLSI Design 2016, 22, 2016
52016
Notice of Removal: FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique
SS Bhairannawar, R Anand, KB Raja, KR Venugopal
2015 International Conference on Electrical, Electronics, Signals …, 2015
52015
FPGA based efficient Multiplier for Image Processing Applications using Recursive Error Free Mitchell Log Multiplier and KOM Architecture
SS Bhairannawar, LM Patnaik
arXiv preprint arXiv:1407.2082, 2014
52014
FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture
SA Naaz, MN Pradeep, S Bhairannawar, S Halvi
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS), 1-5, 2014
52014
FPGA based Recursive Error Free Mitchell Log Multiplier for image Filters
SS Bhairannawar, R Rathan, KB Raja, KR Venugopal, LM Patnaik
Computational Intelligence & Computing Research (ICCIC), 2012 IEEE …, 2012
52012
An Efficient VLSI Architecture for Adaptive Rank Order Filter for Image Noise Removal
MC Hanumantharaju, M Ravishankar, DRR Babu, S Bhairannawar
International journal for Information and Electronics Engineering 1 (1), 2011
52011
Image compression using self organizing map and discrete wavelet transform with error correction
S Raju, SS Bhairannawar
International Journal of Applied Engineering Research 12 (10), 2509-2516, 2017
32017
An Adaptive Threshold based FPGA Implementation for Object and Face Detection
SK HC, S Sarkar, SS Bhairannawar, KB Raja, KR Venugopal
2015 Third International Conference on Image Information Processing (ICIIP …, 2015
32015
An Adaptive Threshold based FPGA Implementation for Object and Face Detection
S Kumar, S Sayantam, SS Bhairannawar, KB Raja, V K R:
IEEE Third International Conference on Image Information Processing, Shimla …, 2015
32015
Efficient FPGA Based Matrix Multiplication Using Mux and Vedic Multiplier
SS Bhairannawar, KB Raja, KR Venugopal, LM Patnaik
International Journal of Computers and technology 12 (5), 2014
32014
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