| A 32 bit mac unit design using vedic multiplier and reversible logic gate R Anitha, N Deshmukh, P Agarwal, SK Sahoo, SP Karthikeyan, ... 2015 International Conference on Circuits, Power and Computing Technologies …, 2015 | 22 | 2015 |
| Braun's multiplier implementation using fpga with bypassing techniques R Anitha, V Bagyaveereswaran International Journal of VLSI Design & Communication Systems 2 (3), 201, 2011 | 14 | 2011 |
| Comparative study of high performance Braun’s multiplier using FPGAs R Anitha, A Nelapati, W Lincy Jesima, V Bagyaveereswaran IOSR J Electron Commun Eng (IOSRJECE) 1, 33-37, 2012 | 12 | 2012 |
| High performance parallel prefix adders with fast carry chain logic R Anitha, V Bagyaveereswaran International Journal of Advanced Research in Engineering and Technology …, 2012 | 12 | 2012 |
| Phytochemical analysis and antibacterial activity of Endophytes of Embelia Tsjeriam cottam Linn CP Chandrappa, R Anitha, P Jyothi, K Rajalakshmi, ... Int J Pharma Bio Sci 3, 201-203, 2013 | 10 | 2013 |
| Smart defrost control for refrigeration system V Bagyaveereswaran, SS Subramanian, R Anitha International Journal of Applied Engineering Research 12 (22), 12202-12207, 2017 | 7 | 2017 |
| Comparative study of Braun’s multiplier using FPGA devices R Anitha, V Bagyaveereswaran Int J Eng Sci Technol (IJEST) 3, 2011 | 6 | 2011 |
| FPGA Implementation of Braun’s Multiplier Using Spartan-3E, Virtex–4, Virtex-5 and Virtex-6 R Anitha, V Bagyaveereswaran Trends in Network and Communications, 486-494, 2011 | 5 | 2011 |
| Simulation of quantum encoder & decoder with flip bit error correction using reversible quantum gates R Anitha, B Vijayalakshmi 2018 International Conference on Recent Trends in Electrical, Control and …, 2018 | 4 | 2018 |
| Automation and On-Line Monitoring Of Effluent Treatment Plant V Bagyaveereswaran, A Vijayan, M Manimozhi, R Anitha International Journal of Chemical Sciences 14 (4), 3167-3178, 2016 | 3 | 2016 |
| Comparative study on transistor based full adder designs R Anitha World Scientific News 3 (53), 404-416, 2016 | 3 | 2016 |
| Sarat Kumar Sahoo (Prof.),” A 32 BIT MAC Unit Design Using Vedic Multiplier and Reversible Logic Gate” in International Conference on Circuit R Anitha Power and Computing Technologies [ICCPCT], 2015 | 3 | 2015 |
| Multiple media based face recognition in unconstrained environments using eigenfaces KR Sreelakshmi, R Anitha, KR Rebitha 2016 International Conference on Next Generation Intelligent Systems (ICNGIS …, 2016 | 2 | 2016 |
| VLSI Implementation of Discrete Linear Convolution using Vedic Mathematics (Real and Complex Numbers) R Anitha, SK Sahoo International Journal of Applied Engineering Research ISSN, 0973-4562, 2016 | 2 | 2016 |
| Image Based Autonomous Navigation for a Lander V Bagyaveereswaran, NN Rajagopal, R Anitha International Journal of Applied Engineering Research 11 (4), 2424-2428, 2016 | 2 | 2016 |
| Effect of heat on antioxidant status of selected green leafy vegetables PR Padma, R Anita Ind J Nutr Dietet 42, 248-258, 2005 | 2 | 2005 |
| FPGA Implementation of Braun’s Multiplier Using Spartan-3E, Virtex–4, Virtex-5 and Virtex-6, Trends in Network and Communications R Anitha, V Bagyaveereswaran Springer, 2003 | 2 | 2003 |
| A systematic hybrid smart region based detection (SRBD) method for object detection R Anitha, S Jayalakshmi 2020 3rd International Conference on Intelligent Sustainable Systems (ICISS …, 2020 | 1 | 2020 |
| Optimal Control of Roll Axis of Aircraft Using PID Controller V Bagyaveereswaran, A Sahu, R Anitha Soft Computing for Problem Solving, 961-969, 2020 | 1 | 2020 |
| Automation of Agricultural Tasks with Robotics-Agrobot V Bagyaveereswaran, A Ghorui, R Anitha 2019 Innovations in Power and Advanced Computing Technologies (i-PACT) 1, 1-7, 2019 | 1 | 2019 |
Sarat Kumar SahooProfessor/HOD , Dept. of Electrical Engineering,Parala Maharaja Engineering College,BerhampurVerified email at pmec.ac.in
