| Low power domino logic circuits in deep-submicron technology using CMOS S Garg, TK Gupta Engineering Science and Technology, an International Journal 21 (4), 625-638, 2018 | 59 | 2018 |
| FDSTDL: Low‐power technique for FinFET domino circuits S Garg, TK Gupta International Journal of circuit Theory and applications 47 (6), 917-940, 2019 | 26 | 2019 |
| A 4: 1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology S Garg, TK Gupta, AK Pandey International Journal of Electronics 107 (4), 513-541, 2020 | 14 | 2020 |
| Low leakage domino logic circuit for wide fan‐in gates using CNTFET S Garg, TK Gupta IET Circuits, Devices & Systems 13 (2), 163-173, 2019 | 13 | 2019 |
| A new technique for designing low power high-speed domino logic circuits in FinFET technology S Garg, T GUPTA Journal of Circuits, Systems and Computers, 2018 | 13 | 2018 |
| Very low power domino logic circuits using carbon nanotube field effect transistor technology S Garg, TK Gupta Journal of Nanoelectronics and Optoelectronics 14 (1), 19-32, 2019 | 10 | 2019 |
| A 1‐bit full adder using CNFET based dual chirality high speed domino logic S Garg, TK Gupta, AK Pandey International Journal of Circuit Theory and Applications 48 (1), 115-133, 2020 | 8 | 2020 |
| SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology S Garg, TK Gupta Journal of Computational Electronics 19, 1249-1267, 2020 | 7 | 2020 |
| A 4: 1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET S Garg, TK Gupta Circuit World 47 (4), 301-324, 2021 | 4 | 2021 |
| Impact of silicon stacked transistors on nano scale domino logic S Garg, TK Gupta, AK Pandey, D Pandey Silicon 14 (14), 8455-8465, 2022 | 3 | 2022 |
| The Effect of Noise Robustness on Domino Using Silicon Nano Materials S Garg, TK Gupta, AK Pandey, D Pandey, P Rajpoot Silicon, 1-15, 2024 | 1 | 2024 |
| BLOOD BANKING VIA CLOUD COMPUTING USING MACHINE LEARNING TRACKING THE BLOOD DONOR LOCATION AT REAL-TIME VR Koli, S Garg, SK Choudhary Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology 54 (4 …, 2022 | 1 | 2022 |
| The assessment of Noise Immunity in Domino Employing Silicon Nano Materials S Garg, TK Gupta, AK Pandey, D Pandey, P Rajput | | 2023 |
| DIABETIC PATIENT MONITORING AND CONTROLLED USING IOT-BASED AND MACHINE LEARNING SYSTEM SK Choudhary, S Garg, VR Koli Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology 54 (4 …, 2022 | | 2022 |
| Child Health Status Monitoring System using IoT VR Koli, S Garg, SK Choudhary IN Patent 202,121,032,911, 2021 | | 2021 |
| Low Noise High Speed Domino Logic Design in Deep Submicron CMOS S Garg, TK Gupta, L Jain, A Jain, A Jain, B Chourasia, A Jain AU Patent 2,021,105,324, 2021 | | 2021 |
| Techniques for Designing Analog Baseband Filter: A Review S Garg, TK Gupta Proceedings of First International Conference on Information and …, 2016 | | 2016 |
| Efficient domino logic circuits design with Nano FET technologies S Garg Bhopal, 0 | | |
tarun guptaAssistant Professor of Electronics and Communication Engineering, MANIT, BhopalVerified email at manit.ac.in
