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Khyamling Parane
Khyamling Parane
Verified email at nitk.edu.in
Title
Cited by
Cited by
Year
Cloud based intelligent healthcare monitoring system
KA Parane, NC Patil, SR Poojara, TS Kamble
2014 international conference on issues and challenges in intelligent …, 2014
442014
YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAs
P Prasad, K Parane, B Talawar
2018 31st International Conference on VLSI Design and 2018 17th …, 2018
112018
FPGA based noc simulation acceleration framework supporting adaptive routing
K Parane, P Prabhu, B Talawar
2018 IEEE International Conference on Electronics, Computing and …, 2018
102018
Internet-of-things and mobile application based hybrid model for controlling energy system
MA Patil, K Parane, S Poojara, A Patil
International Journal of Information Technology 13 (5), 2129-2138, 2021
92021
LBNoC: Design of low-latency router architecture with lookahead bypass for network-on-chip using FPGA
K Parane, B Talawar
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2020
82020
Design of an adaptive and reliable network on chip router architecture using FPGA
K Parane, BMP Prasad, B Talawar
2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019
72019
FPGA friendly NoC simulation acceleration framework employing the hard blocks
BMP Prasad, K Parane, B Talawar
Computing, 1-23, 2021
62021
An efficient FPGA-based network-on-chip simulation framework utilizing the hard blocks
BM Prabhu Prasad, K Parane, B Talawar
Circuits, Systems, and Signal Processing 39 (10), 5247-5271, 2020
62020
High-performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs
P Prasad, K Parane, B Talawar
20th international symposium on quality electronic design (ISQED), 163-169, 2019
62019
Trace-driven simulation and design space exploration of network-on-chip topologies on FPGA
GS Sangeetha, V Radhakrishnan, P Prasad, K Parane, B Talawar
2018 8th International Symposium on Embedded Computing and System Design …, 2018
62018
Optimization of CI engine performance parameters for jatropha biodiesel blending fuel by using ANN software
GH Kawade, ST Satpute, KA Parane
International Research journal of engineering and technology 2 (03), 1151-1156, 2015
62015
High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks
BMP Prasad, K Parane, B Talawar
2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019
52019
YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs
K Parane, BM Prabhu Prasad, B Talawar
Journal of Circuits, Systems and Computers 28 (12), 1950202, 2019
42019
P-noc: performance evaluation and design space exploration of nocs for chip multiprocessor architecture using fpga
K Parane, BM Prabhu Prasad, B Talawar
Wireless Personal Communications 114 (4), 3295-3319, 2020
32020
Cloud computing for agent-based traffic management systems
MA Patil, KA Parane, D Rajesh
ICRTITCS-2012, proceedings published in international journal of computer …, 2012
32012
MuteTrans: A communication medium for deaf
NC Patil, KA Parane, MV Guruprasad, SR Poojara
2014 IEEE International Advance Computing Conference (IACC), 106-111, 2014
22014
Smart Attendance Management System using IoT
MA Patil, K Parane, DD Sivaprasad, S Poojara, MR Lamani
2022 Second International Conference on Computer Science, Engineering and …, 2022
12022
Hy-BTree: An efficient Tree based topology for FPGA based NoC implementation
BMP Prasad, K Parane, B Talawar
2021 IEEE International Conference on Electronics, Computing and …, 2021
12021
Analysis of cache behaviour and software optimizations for faster on-chip network simulations
BMP Prasad, K Parane, B Talawar
International Journal of System Assurance Engineering and Management 10, 696-712, 2019
12019
Cache analysis and software optimizations for faster on-chip network simulations
K Parane, BMP Prasad, B Talawar
2016 11th International Conference on Industrial and Information Systems …, 2016
12016
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