Bishnu  Prasad De, PhD
Bishnu Prasad De, PhD
Assistant Professor, School of Electronics Engineering, KIIT University, Bhubaneswar,India
Verified email at kiit.ac.in
TitleCited byYear
Optimal selection of components value for analog active filter design using simplex particle swarm optimization
BP De, R Kar, D Mandal, SP Ghoshal
International Journal of Machine Learning and Cybernetics 6 (4), 621-636, 2015
282015
Particle swarm optimization with aging leader and challengers for optimal design of analog active filters
BP De, R Kar, D Mandal, SP Ghoshal
Circuits, Systems, and Signal Processing 34 (3), 707-737, 2015
172015
An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm
BP De, R Kar, D Mandal, SP Ghoshal
International Journal of Machine Learning and Cybernetics, 1-20, 2015
162015
Optimal analog active filter design using craziness‐based particle swarm optimization algorithm
BP De, R Kar, D Mandal, SP Ghoshal
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2015
152015
PSO with aging leader and challengers for optimal design of high speed symmetric switching CMOS inverter
BP De, R Kar, D Mandal, SP Ghoshal
International Journal of Machine Learning and Cybernetics, 1-20, 2016
102016
Optimal design of high speed symmetric switching CMOS inverter using hybrid harmony search with differential evolution
BP De, R Kar, D Mandal, SP Ghoshal
Soft Computing 20 (9), 3699-3717, 2016
92016
Design of symmetric switching CMOS inverter using PSOCFIWA
B P De, R Kar, D Mandal, SP Ghoshal
Communications and Signal Processing (ICCSP), 2014 International Conference …, 2014
72014
Design of Optimal CMOS Analog Amplifier Circuits Using a Hybrid Evolutionary Optimization Technique
BP De, KB Maji, R Kar, D Mandal, SP Ghoshal
Journal of Circuits, Systems, and Computers, 1850029, 2017
52017
Soft computing-based approach for optimal design of on-chip comparator and folded-cascode op-amp using colliding bodies optimization
BP De, R Kar, D Mandal, SP Ghoshal
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2016
42016
Optimal CMOS inverter design using differential evolution algorithm
BP De, R Kar, D Mandal, SP Ghoshal
Journal of Electrical Systems and Information Technology 2 (2), 219-241, 2015
42015
Application of Improved PSO for Optimal Design of CMOS Two-stage Op-amp using Nulling Resistor Compensation Circuit
BP De, KB Maji, R Kar, D Mandal, SP Ghoshal
2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani …, 2017
32017
Optimal high speed CMOS inverter design using craziness based Particle Swarm Optimization Algorithm
BP De, R Kar, D Mandal, SP Ghoshal
Open Engineering 5 (1), 2015
32015
Optimal Design of Low-Voltage, Two-Stage CMOS Op-amp Using Evolutionary Techniques
BP De, KB Maji, B Bag, S Tripathi, R Kar, D Mandal, SP Ghoshal
Lecture Notes in Electrical Engineering 470, 303-315, 2018
22018
Optimal Switching Characterization of High Speed CMOS Inverter Design Using Social Emotional Optimization Algorithm
KB Maji, BP De, R Kar, D Mandal, SP Ghoshal
JOURNAL OF ENGINEERING SCIENCE AND TECHNOLOGY REVIEW 11 (2), 182-195, 2018
12018
Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit
BP De, KB Maji, R Kar, D Mandal, SP Ghoshal
International Journal of High Speed Electronics and Systems 26 (04), 1702003 …, 2017
12017
Optimization of Electrical Parameters for the Gate Stack Double Gate (GSDG) Mosfet Using PSO Variants
D Chowdhury, BP De, KB Maji, SGR Kar, D Mandal, S Bhunia
International Journal of Nanoscience, 2019
2019
CMOS Analog Amplifier Circuits Design Using Seeker Optimization Algorithm
KB Maji, BP De, R Kar, D Mandal, SP Ghoshal
IETE Journal of Research, 1-10, 2019
2019
Optimization of Electrical Parameters for the Gate Stack Double Gate (GSDG) MOSFET using Simplex-PSO Algorithm
D Chowdhury, BP De, KB Maji, S Ghosh, R Kar, D Mandal
2019 Devices for Integrated Circuit (DevIC), 23-24 March, 2019, Kalyani …, 2019
2019
Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithm
S Ghosh, BP De, R Kar, D Mandal, AK Mal
Journal of Computational Electronics 18 (2), 737-747, 2019
2019
Symbiotic Organisms Search Algorithm for Optimal Design of CMOS Two-stage Op-amp with Nulling Resistor and Robust Bias Circuit
S Ghosh, BP De, R Kar, AK Mal
IET Circuits, Devices & Systems, 1-10, 2019
2019
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Articles 1–20