| An optimal allocation of carry-save-adders in arithmetic circuits J Um, T Kim IEEE Transactions on Computers 50 (3), 215-233, 2001 | 44 | 2001 |
| A practical approach to the synthesis of arithmetic circuits using carry-save-adders T Kim, J Um IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000 | 39 | 2000 |
| In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem WC Kwon, S Yoo, J Um, SW Jeong 2009 Design, Automation & Test in Europe Conference & Exhibition, 1058-1063, 2009 | 37 | 2009 |
| Optimal allocation of carry-save-adders in arithmetic optimization J Um, T Kim, CL Liu 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 31 | 1999 |
| Layout-driven resource sharing in high-level synthesis J Um, J Kim, T Kim Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 30 | 2002 |
| System on chip improving data traffic and operating method thereof WC Kwon, JG Yun, B Jeong, JH Um, HJ Kang US Patent 8,943,249, 2015 | 20 | 2015 |
| OSFA: A new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions S Roy, D Liu, J Singh, J Um, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 19 | 2016 |
| Layout-aware synthesis of arithmetic circuits J Um, T Kim Proceedings of the 39th annual Design Automation Conference, 207-212, 2002 | 17 | 2002 |
| OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions S Roy, D Liu, J Um, DZ Pan Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 16 | 2015 |
| System-on-chip and data arbitration method thereof B Jeong, J Yun, J Um, JS Lee, HJ Kang, S Hong, LL Liao US Patent 8,819,310, 2014 | 16 | 2014 |
| A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis J Um, T Kim, CL Liu Proceedings of the 37th Annual Design Automation Conference, 98-103, 2000 | 10 | 2000 |
| Optimal bit-level arithmetic optimisation for high-speed circuits J Um, T Kim Electronics Letters 36 (5), 405-407, 2000 | 9 | 2000 |
| System On Chip Keeping Load Balance And Load Balancing Method Thereof J Yun, B Jeong, J Um, HJ Kang, S Hong US Patent App. 13/178,666, 2012 | 7 | 2012 |
| A systematic IP and bus subsystem modeling for platform-based system design J Um, WC Kwon, S Hong, YT Kim, KM Choi, JT Kong, SK Eo, T Kim Proceedings of the Design Automation & Test in Europe Conference 1, 5 pp., 2006 | 7 | 2006 |
| Vip: A practical approach to platform-based system modeling methodology JH Um, SP Hong, YT Kim, E Chung, KM Choi, JT Kong, SK Eo JSTS: Journal of Semiconductor Technology and Science 5 (2), 89-101, 2005 | 7 | 2005 |
| Asynchronous upsizing circuit in data processing system J Yun, J Um, W Kwon, HJ Kang, B Jeong US Patent 8,443,122, 2013 | 6 | 2013 |
| Synthesis of arithmetic circuits considering layout effects J Um, T Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 6 | 2003 |
| Bandwidth synchronization circuit and bandwidth synchronization method J Yun, H Jung, J Um, S Shim, S Hong, B Jeong US Patent 8,582,709, 2013 | 4 | 2013 |
| Interface Devices And Systems Including The Same JG Yun, JH Um, HU Jung, S Hong, JS Lee, HJ Kang, LL Liao, W Kwon US Patent App. 13/287,339, 2012 | 4 | 2012 |
| A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper) T Kim, J Um Proceedings of the 2000 Asia and South Pacific Design Automation Conference …, 2000 | 4 | 2000 |
