| Trading accuracy for power with an underdesigned multiplier architecture P Kulkarni, P Gupta, M Ercegovac 2011 24th Internatioal Conference on VLSI Design, 346-351, 2011 | 653 | 2011 |
| Trading accuracy for power in a multiplier architecture P Kulkarni, P Gupta, MD Ercegovac Journal of Low Power Electronics 7 (4), 490-501, 2011 | 159 | 2011 |
| A methodology for the early exploration of design rules for multiple-patterning technologies RS Ghaida, T Sahu, P Kulkarni, P Gupta Proceedings of the International Conference on Computer-Aided Design, 50-56, 2012 | 13 | 2012 |
| Navigo--Accessibility Solutions for Cerebral Palsy Affected H Pokhariya, P Kulkarni, V Kantroo, T Jindal 2006 International Conference on Computational Inteligence for Modelling …, 2006 | 9 | 2006 |
| Minimizing clock domain crossing in Network on Chip interconnect P Kulkarni, P Gupta, R Beraha Fifteenth International Symposium on Quality Electronic Design, 292-299, 2014 | 2 | 2014 |
| BiDIFS and CoDEBTS: Exploiting Compiler-Processor Interaction for Performance Enhancement P Aditya, P Kulkarni TENCON 2008-2008 IEEE Region 10 Conference, 1-6, 2008 | | 2008 |
PUNEET GUPTAUCLA Electrical and Computer EngineeringVerified email at g.ucla.edu
