| Spintronic devices: a promising alternative to CMOS devices P Barla, VK Joshi, S Bhat Journal of Computational Electronics 20 (2), 805-837, 2021 | 144 | 2021 |
| From MTJ device to hybrid CMOS/MTJ circuits: A review VK Joshi, P Barla, S Bhat, BK Kaushik IEEE Access 8, 194105-194146, 2020 | 55 | 2020 |
| A novel low power and reduced transistor count magnetic arithmetic logic unit using hybrid STT-MTJ/CMOS circuit P Barla, VK Joshi, S Bhat IEEE Access 8, 6876-6889, 2020 | 34 | 2020 |
| Design and analysis of LIM hybrid MTJ/CMOS logic gates P Barla, D Shet, VK Joshi, S Bhat 2020 5th International Conference on Devices, Circuits and Systems (ICDCS …, 2020 | 15 | 2020 |
| A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure P Barla, VK Joshi, S Bhat Ain Shams Engineering Journal 12 (2), 1839-1847, 2021 | 12 | 2021 |
| Design and analysis of SHE-assisted STT MTJ/CMOS logic gates P Barla, VK Joshi, S Bhat Journal of Computational Electronics 20 (5), 1964-1976, 2021 | 11 | 2021 |
| Fully nonvolatile hybrid full adder based on SHE+ STT-MTJ/CMOS LIM architecture P Barla, VK Joshi, S Bhat IEEE Transactions on Magnetics 58 (9), 1-11, 2022 | 8 | 2022 |
| Design of a novel non‐volatile hybrid spintronic true random number generator S Jape, VK Joshi, P Barla International Journal of Circuit Theory and Applications 50 (5), 1487-1501, 2022 | 3 | 2022 |
| Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure P Barla, VK Joshi, S Bhat Journal of Circuits, Systems and Computers 31 (08), 2250146, 2022 | 2 | 2022 |
| A novel auto-write-stopping circuit for SHE+ STT-MTJ/CMOS hybrid ALU P Barla, VK Joshi, S Bhat IEEE Transactions on Electron Devices 69 (4), 1683-1690, 2022 | 2 | 2022 |
| Design and evaluation of hybrid SHE+ STT-MTJ/CMOS full adder based on LIM architecture P Barla, VK Joshi, S Bhat IOP Conference Series: Materials Science and Engineering 1187 (1), 012015, 2021 | 2 | 2021 |
| Design and analysis of self-write-terminated hybrid STT-MTJ/CMOS logic gates using LIM architecture P Barla, VK Joshi, S Bhat 2021 IEEE International Conference on Distributed Computing, VLSI …, 2021 | 1 | 2021 |
| Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation P Barla, H Shivarama, G Deepa, U Ujjwal Journal of Low Power Electronics and Applications 14 (1), 3, 2024 | | 2024 |
| Exploitation of Metadata for Custom-Made Image Explore R Shetty, P Barla | | |
| LAB-VIEW BASED LINEAR FILTERING APPROACH TO DIGITAL DTMF DETECTION USING GOERTZEL ALGORITHM MRP KUMAR, MR GANDHIMATHINATHAN, MRP BARLA “Recent Trends in Electronics & Communication Engineering”(NCEC-2010), 70, 0 | | |
| Design and Simulation of FM Band Tunable Analog Filter using NMOS Varactors P Barla | | |
| Design of a High Speed FPGA Network Intrusion Detection System S Naik, P Barla | | |
