| Effect of temperature on performance of 5-nm node silicon nanosheet transistors for analog applications YP Pundir, A Bisht, R Saha, PK Pal Silicon 14 (16), 10581-10589, 2022 | 8 | 2022 |
| Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor YP Pundir, A Bisht, R Saha, PK Pal Semiconductor Science and Technology 36 (9), 095037, 2021 | 8 | 2021 |
| DWT chip design and FPGA synthesis for image processing A Bisht, A Kumar Int J Recent Technol Eng (IJRTE) 8, 1-10, 2019 | 4 | 2019 |
| Chip Design of DWT for Image Compression A Bisht, M Gupta International Research Journal of Engineering and Technology 2 (4), 320-324, 2015 | 2 | 2015 |
| Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications A Bisht, YP Pundir, PK Pal Analog Integrated Circuits and Signal Processing 116 (1-2), 35-47, 2023 | 1 | 2023 |
| Effect of process-induced variations on analog performance of silicon based nanosheet transistor YP Pundir, A Bisht, R Saha, PK Pal Silicon 15 (10), 4449-4455, 2023 | 1 | 2023 |
| Power supply variations and analog performance of 5-nm node silicon Nanosheet transistor YP Pundir, A Bisht, R Saha, AS Bahuguna, K Kumar, PK Pal 2022 International Conference on Advances in Computing, Communication and …, 2022 | 1 | 2022 |
| Electro-Thermal analysis of vertically stacked gate all around nano-sheet transistor A Bisht, YP Pundir, PK Pal international symposium on VLSI design and test, 126-136, 2022 | 1 | 2022 |
| Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study A Bisht, YP Pundir, PK Pal Silicon 15 (12), 5175-5185, 2023 | | 2023 |
