Follow
Jai Gopal Pandey, Ph.D.
Jai Gopal Pandey, Ph.D.
Senior Principal Scientist, CSIR– Central Electronics Engg. Research Insti (CEERI), Pilani, India
Verified email at ceeri.res.in - Homepage
Title
Cited by
Cited by
Year
A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher
JG Pandey, SM IEEE, T Goel, A Karmakar
in Proceeding: 31st International Conference on VLSI Design and 2018 17th …, 2018
282018
An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications
S Khan, AP Shah, N Gupta, SS Chouhan, JG Pandey, SK Vishvakarma
Microelectronics journal 92, 104605, 2019
232019
Hardware architectures for PRESENT block cipher and their FPGA implementations
JG Pandey, T Goel, A Karmakar
IET Circuits, Devices & Systems 13 (7), 958-969, 2019
232019
Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications
S Khan, AP Shah, SS Chouhan, S Rani, N Gupta, JG Pandey, ...
Analog Integrated Circuits and Signal Processing 103 (3), 477-492, 2020
182020
A novel architecture for FPGA implementation of Otsu's global automatic image thresholding algorithm
JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
182014
An efficient VLSI architecture for PRESENT block cipher and its FPGA implementation
JG Pandey, T Goel, A Karmakar
VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017
172017
Platform-Based Extensible Hardware-Software Video Streaming Module for a Smart Camera System
JG Pandey, S Purushottam, A Karmakar, C Shekhar
International Journal of Modeling and Optimization 2 (4), 482-487, 2012
162012
A symmetric D flip-flop based PUF with improved uniqueness
S Khan, AP Shah, SS Chouhan, N Gupta, JG Pandey, SK Vishvakarma
Microelectronics Reliability 106, 113595, 2020
152020
An Efficient VLSI Architecture for Data Encryption Standard and its FPGA Implementation
JG Pandey, SM IEEE, A Gurawa, H Nehra, A Karmakar
2nd IEEE Int’l Conf. on VLSI Systems, Architecture, Technology and …, 2016
152016
An FPGA-based fixed-point architecture for binary logarithmic computation
JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan
2013 IEEE Second International Conference on Image Information Processing …, 2013
142013
GIFT Cipher Usage in Image Data Security: Hardware Implementations, Performance and Statistical Analyses
A Jangir, JG Pandey
Journal of Real-Time Image Processing, 2021
132021
Platform-Based Design Approach for Embedded Vision Applications
JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan
Journal of Image and Graphics 1 (1), 1-6, 2013
122013
An RNS Implementation of the Elliptic Curve Cryptography for IoT Security
JG Pandey, C Mitharwal, A Karmakar
IEEE International Conference on Trust, Privacy and Security in Intelligent …, 2019
102019
An FPGA-based architecture for local similarity measure for image/video processing applications
JG Pandey, A Karmakar, C Shekhar, S Gurunarayanan
2015 28th international conference on VLSI design, 339-344, 2015
102015
Implementation of an Improved Connected Component Labeling Algorithm using FPGA-based Platform
JG Pandey, A Karmakar, AK Mishra, C Shekhar, S Gurunarayanan
Signal Processing and Communications (SPCOM), 2014 International Conference …, 2014
102014
Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform
JG Pandey, A Karmakar
International Journal of Electronics 106 (3), 455-476, 2019
82019
A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA
JG Pandey, A Laddha, SD Samaddar
24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar …, 2020
72020
A unified architecture for AES/PRESENT ciphers and its usage in an SoC environment
JG Pandey, S Gupta, A Karmakar
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020
72020
A novel design of SRAM using memristors at 45 nm technology
V Jeffry Louis, J Gopal Pandey
VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019
72019
A high-performance VLSI architecture of the PRESENT cipher and its implementations for SoCs
JG Pandey, T Goel, M Nayak, C Mitharwal, A Karmakar, R Singh
2018 31st IEEE International System-on-Chip Conference (SOCC), 96-101, 2018
72018
The system can't perform the operation now. Try again later.
Articles 1–20