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Pranab Kishore Dutta
Pranab Kishore Dutta
Verified email at nerist.ac.in - Homepage
Title
Cited by
Cited by
Year
Analytical modeling of linearly graded alloy material gate recessed ultra thin body source/drain SON MOSFET
PK Dutta, B Manna, SK Sarkar
Superlattices and Microstructures 77, 64-75, 2015
132015
Analytical modeling of a high-K underlap dielectric-and charge-modulated silicon-on-nothing FET-based biosensor
KN Singh, PK Dutta
Journal of Computational Electronics 19 (3), 1126-1135, 2020
122020
Ultralow power, noise immune stacked‐double stage clocked‐inverter domino technique for ultradeep submicron technology
SR Ghimiray, P Meher, PK Dutta
International Journal of Circuit Theory and Applications 46 (11), 1953-1967, 2018
82018
Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation
J Bag, S Roy, PK Dutta, SK Sarkar
IETE Journal of Research 60 (5), 355-363, 2014
72014
Analytical modeling of underlap graded channel field effect transistor as a label-free biosensor
KN Singh, PK Dutta
Superlattices and Microstructures 155, 106897, 2021
62021
An improved charge‐sharing elimination pseudo‐domino logic
SR Ghimiray, P Meher, PK Dutta
International Journal of Circuit Theory and Applications 48 (8), 1346-1362, 2020
62020
Implementation of Universal Gates (NAND) Based on Nano-Magnetic Logic Using Multiferroics
A Sarkar, PK Dutta, A Ghosh, S Ray, SK Sarkar
Quantum Matter 5 (4), 505-509, 2016
42016
Analysis and simulation of dual metal double gate son mosfet using hafnium dioxide for better performance
PK Dutta, N Bagga, K Naskar, SK Sarkar
IET Digital Library, 2015
42015
Threshold voltage roll-off and DIBL model for DMDG SON MOSFET: a quantum study
S Shee, G Bhattacharyya, PK Dutta, SK Sarkar
Proceedings of the 2014 IEEE Students' Technology Symposium, 381-385, 2014
42014
Quantum confinement effects in the subthreshold characteristics of short-channel DMDG MOSFET
S Shee, G Bhattacharyya, PK Dutta, SK Sarkar
Proceedings of The 2014 International Conference on Control, Instrumentation…, 2014
42014
Design and implementation of 4-bit ripple carry adder using SETMOS architecture
D Rajkumar, PK Dutta, SK Sarkar
2016 IEEE International Conference on Recent Trends in Electronics…, 2016
32016
Analytical Investigation of a Split Double Gate Graded Channel Field Effect Transistor for Biosensing Applications
KN Singh, PK Dutta
Silicon, 1-11, 2022
22022
Analytical Design of FET-Based Biosensors
KN Singh, PK Dutta
Advanced VLSI Design and Testability Issues, 147-167, 2020
22020
Review and Analysis of Charge-Pump Phase-Locked Loop
M Gogoi, PK Dutta
Electronic Systems and Intelligent Computing, 565-574, 2020
22020
Comparative Analysis of Underlapped Silicon on Insulator and Underlapped Silicon on Nothing Dielectric and Charge Modulated FET based Biosensors
KN Singh, PK Dutta
2019 Devices for Integrated Circuit (DevIC), 231-235, 2019
22019
Error probability independent delay analysis of single electronics circuits
A Jain, A Ghosh, PK Dutta, NB Singh, SK Sarkar
International Journal of Circuit Theory and Applications 46 (2), 290-298, 2018
22018
Energy efficient, noise immune 4 4 Vedic multiplier using semi-domino logic style
SR Ghimiray, P Meher, PK Dutta
Region 10 Conference, TENCON 2017-2017 IEEE, 1037-1041, 2017
22017
Quantum analytical modeling and simulation of CNT on insulator (COI) and CNT on nothing (CON) FET: a comparative analysis
S Mukherjee, D Bandyopadhyay, PK Dutta, SK Sarkar
Journal of Theoretical and Applied Physics 10 (2), 91-97, 2016
22016
A Comparative Study for Disease Identification from Heart Auscultation using FFT, Cepstrum and DCT Correlation Coefficients
S Majumder, S Pal, PK Dutta
13th International Conference on Biomedical Engineering, 754-757, 2009
22009
DESIGN OF A FOUR STAGES VCO USING A NOVEL DELAY CIRCUIT FOR OPERATION IN DISTRIBUTED BAND FREQUENCIES
M Gogoi, PK Dutta
Facta Universitatis, Series: Electronics and Energetics 35 (4), 469-482, 2022
12022
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Articles 1–20