| Hypotensive activity and toxicology of constituents from Bombax ceiba stem bark R Saleem, SI Ahmad, M Ahmed, Z Faizi, S Zikr-ur-Rehman, M Ali, S Faizi Biological and Pharmaceutical Bulletin 26 (1), 41-46, 2003 | 102 | 2003 |
| Efficient kernel functions for support vector machine regression model for analog circuits’ performance evaluation D Boolchandani, A Ahmed, V Sahula Analog Integrated Circuits and Signal Processing 66, 117-128, 2011 | 28 | 2011 |
| TSV-and delay-aware 3D-IC floorplanning MA Ahmed, S Mohapatra, M Chrzanowska-Jeske Analog Integrated Circuits and Signal Processing 87, 235-248, 2016 | 18 | 2016 |
| Delay and power optimization with TSV-aware 3D floorplanning MA Ahmed, M Chrzanowska-Jeske Fifteenth International Symposium on Quality Electronic Design, 189-196, 2014 | 18 | 2014 |
| Cybercrime challenges in Iraqi Academia: creating digital awareness for preventing cybercrimes KM Tarrad, H Al-Hareeri, T Alghazali, M Ahmed, MKA Al-Maeeni, ... International Journal of Cyber Criminology 16 (2), 15–31-15–31, 2022 | 11 | 2022 |
| Logical effort framework for CNFET-based VLSI circuits for delay and area optimization M Ali, MA Ahmed, M Chrzanowska-Jeske IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (3), 573-586, 2018 | 10 | 2018 |
| TSVs in early layout design exploration for 3D ICs MA Ahmed, M Chrzanowska-Jeske 2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014 | 10 | 2014 |
| Logical Effort model for CNFET circuits with CNTs variations M Ali, M Ahmed, M Chrzanowska-Jeske, J Morris 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 1218-1221, 2015 | 8 | 2015 |
| Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes M Ali, M Ahmed, M Chrzanowska-Jeske 2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014 | 7 | 2014 |
| TSV capacitance aware 3-D floorplanning MA Ahmed, M Chrzanowska-Jeske 2013 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2013 | 7 | 2013 |
| Improved support vector machine regression for analog circuits macromodeling using efficient kernel functions D Boolchandani, A Ahmed, V Sahula IEEE International Workshop on Symbolic and Numerical Methods, Modeling and …, 2008 | 7 | 2008 |
| Fast and accurate evaluation of delay in CNFET circuits M Ali, M Ahmed, M Chrzanowska-Jeske 2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO), 659-662, 2016 | 6 | 2016 |
| Buffered interconnects in 3D IC layout design MA Ahmed, S Mohapatra, M Chrzanowska-Jeske Proceedings of the 18th System Level Interconnect Prediction Workshop, 1-8, 2016 | 5 | 2016 |
| 3D floorplanning with nets-to-TSVs assignment MA Ahmed, S Mohapatra, M Chrzanowska-Jeske 2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014 | 5 | 2014 |
| Logical effort model for CNFET-based circuits M Ali, M Ahmed, M Chrzanowska-Jeske 14th IEEE International Conference on Nanotechnology, 460-465, 2014 | 4 | 2014 |
| Early layout design exploration in TSV-based 3D integrated circuits MA Ahmed | 3 | 2017 |
| Dynamic nets-to-TSVs assignment in 3D floorplanning MA Ahmed, S Mohapatra, M Chrzanowska-Jeske 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1870-1873, 2015 | 3 | 2015 |
| Power efficiency of 3D vs 2D ICs M Chrzanowska-Jeske, MA Ahmed 2013 IEEE Faible Tension Faible Consommation, 1-4, 2013 | 3 | 2013 |
| Iraqi Contract Law and Sharia Law: A Blended Concept FAM Dahash, AA Hasan, M Ahmed, AA Sabti, RS Shaker, WN Abood, ... International Journal of Criminal Justice Sciences 17 (1), 151–161-151–161, 2022 | 2 | 2022 |
| Fast floorplanning for fixed-outline and nonrectangular regions MA Ahmed, S Pinge, M Chrzanowska-Jeske 2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012 | 2 | 2012 |
