| Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs SK Swain, A Dutta, S Adak, SK Pati, CK Sarkar Microelectronics Reliability 61, 24-29, 2016 | 41 | 2016 |
| Influence of barrier thickness on AlInN/GaN underlap DG MOSFET device performance H Pardeshi, G Raj, S Pati, N Mohankumar, CK Sarkar Superlattices and Microstructures 60, 47-59, 2013 | 37 | 2013 |
| High performance AlInN/AlN/GaN p-GaN back barrier gate-recessed enhancement-mode HEMT S Adak, A Sarkar, S Swain, H Pardeshi, SK Pati, CK Sarkar Superlattices and Microstructures 75, 347-357, 2014 | 36 | 2014 |
| Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET H Pardeshi, SK Pati, G Raj, N Mohankumar, CK Sarkar Journal of Semiconductors 33 (12), 124001, 2012 | 26 | 2012 |
| Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs SK Pati, K Koley, A Dutta, N Mohankumar, CK Sarkar Microelectronics Reliability 54 (6-7), 1137-1142, 2014 | 25 | 2014 |
| Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs SK Swain, S Adak, SK Pati, CK Sarkar Superlattices and Microstructures 97, 258-267, 2016 | 24 | 2016 |
| Performance assessment of gate material engineered AlInN/GaN underlap DG MOSFET for enhanced carrier transport efficiency HM Pardeshi, G Raj, S Pati, N Mohankumar, CK Sarkar Superlattices and Microstructures 60, 10-22, 2013 | 24 | 2013 |
| Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage S Adak, SK Swain, A Singh, H Pardeshi, SK Pati, CK Sarkar Physica E: Low-dimensional Systems and Nanostructures 64, 152-157, 2014 | 19 | 2014 |
| Impact of gate length and barrier thickness on performance of InP/InGaAs based double gate metal–oxide-semiconductor heterostructure field-effect transistor (DG MOS-HFET) SK Pati, H Pardeshi, G Raj, NM Kumar, CK Sarkar Superlattices and Microstructures 55, 8-15, 2013 | 19 | 2013 |
| Polarization based charge density drain current and small-signal model for nano-scale AlInGaN/AlN/GaN HEMT devices D Godwinraj, H Pardeshi, SK Pati, N Mohankumar, CK Sarkar Superlattices and Microstructures 54, 188-203, 2013 | 18 | 2013 |
| Effect of channel thickness and doping concentration on sub-threshold performance of Graded Channel and gate stack DG MOSFETs SK Swain, S Adak, B Sharma, SK Pati, CK Sarkar Journal of Low Power Electronics 11 (3), 366-372, 2015 | 15 | 2015 |
| Investigation of asymmetric effects due to gate misalignment, gate bias and underlap length in III–V heterostructure underlap DG MOSFET H Pardeshi, SK Pati, G Raj, N Mohankumar, CK Sarkar Physica E: Low-dimensional Systems and Nanostructures 46, 61-67, 2012 | 15 | 2012 |
| Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs H Pardeshi, G Raj, SK Pati, N Mohankumar, CK Sarkar Semiconductors 46, 1299-1303, 2012 | 14 | 2012 |
| Study of analog/Rf and stability investigation of surrounded gate junctionless graded channel MOSFET (SJLGC MOSFET) S Misra, SM Biswal, B Baral, SK Swain, SK Pati Silicon, 1-12, 2021 | 9 | 2021 |
| Comparison study of Drain Current, Subthreshold Swing and DIBL of III-V Heterostructure and Silicon Double Gate MOSFET SKP Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar IJECT 4 (Spl-1), 33-35, 2013 | 5* | 2013 |
| Study of effect of downscaling on the analog/RF performance of gate all around JLMOSFET S Misra, SM Biswal, B Bara, SK Swain, SK Pati 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 234-241, 2018 | 4 | 2018 |
| Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region SK Pati, H Pardeshi, G Raj, N Mohankumar, CK Sarkar Journal of Semiconductors 34 (2), 024002, 2013 | 3 | 2013 |
| Analytical modelling of a Cyl-JLAM MOSFET in the subthreshold region using distinct device geometry S Misra, SM Biswal, B Baral, SK Swain, A Sarkar, SK Pati Journal of Computational Electronics 20, 480-491, 2021 | 2 | 2021 |
| Performance analysis of down scaling effect of Si based SRG tunnel FET SM Biswal, B Baral, SK Swain, SK Pati 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 344-348, 2018 | 2 | 2018 |
| Analysis of flicker and thermal noise in p-channel Underlap DG FinFET SK Swain, S Adak, SK Pati, H Pardeshi, CK Sarkar Microelectronics Reliability 54 (8), 1549-1554, 2014 | 2 | 2014 |
Hemant PardeshiGovernment Polytechnic, NasikVerified email at mahaurja.com
