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Sagar Satapathy
Sagar Satapathy
Applications Engineer, Synopsys
Verified email at synopsys.com
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Cited by
Year
Sam: A segmentation based approximate multiplier for error tolerant applications
D Pandey, S Singh, V Mishra, S Satapathy, DS Banerjee
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
102021
Efcsa: An efficient carry speculative approximate adder with rectification
S Singh, V Mishra, S Satapathy, D Pandey, K Goswami, DS Banerjee, ...
2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-7, 2022
52022
HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications
D Pandey, V Mishra, S Singh, S Satapathy, B Jajodia, DS Banerjee
2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-5, 2022
32022
Art-mac: Approximate rounding and truncation based mac unit for fault-tolerant applications
V Mishra, D Pandey, S Singh, S Satapathy, K Goswami, B Jajodia, ...
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1640-1644, 2022
22022
A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices
K Goswami, S Das, S Satapathy, DS Banerjee
Proceedings of the 2022 International Symposium on Memory Systems, 1-16, 2022
2022
AxLEAP: Enabling Low-Power Approximations Through Unified Power Format
S Satapathy, S Singh, K Goswami, V Mishra, D Pandey, DS Banerjee
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1645-1649, 2022
2022
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