| Energy conservation in WSN through multilevel data reduction scheme M Arunraja, V Malathi, E Sakthivel Microprocessors and Microsystems 39 (6), 348-357, 2015 | 28 | 2015 |
| Distributed similarity based clustering and compressed forwarding for wireless sensor networks M Arunraja, V Malathi, E Sakthivel ISA transactions 59, 180-192, 2015 | 15 | 2015 |
| Collective prediction exploiting spatio temporal correlation (CoPeST) for energy efficient wireless sensor networks M Arunraja, V Malathi KSII Transactions on Internet and Information Systems (TIIS) 9 (7), 2488-2511, 2015 | 13 | 2015 |
| MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture E Sakthivel, V Malathi, M Arunraja Microprocessors and Microsystems 38 (7), 692-706, 2014 | 13 | 2014 |
| Distributed energy efficient clustering algorithm for wireless sensor networks M Arunraja, V Malathi, E Sakthivel Informacije Midem 45 (3), 180-187, 2015 | 10 | 2015 |
| VELAN: variable energy aware sense amplifier link for asynchronous network on chip E Sakthivel, V Malathi, M Arunraja Circuits and Systems 7 (3), 128-144, 2016 | 3 | 2016 |
| A New Simulator Based on Multi Core Processor with Improved Sense Amplifier E Sakthivel, V Malathi, M Arunraja Journal of Circuits, Systems and Computers 24 (09), 1550141, 2015 | 3 | 2015 |
| An Adaptive Prediction Framework for Energy Efficient Wireless Sensor Networks. M Arunraja, V Malathi, E Sakthivel Adhoc & Sensor Wireless Networks 33, 2016 | 2 | 2016 |
| NABI: low power, high speed FPGA based novel approach for bilateral filter E Sakthivel, V Malalthi, M Arunraja, G Perumalvignesh Intl. J. Innovation and Scientific Res 25 (2), 646-653, 2016 | 2 | 2016 |
| Butha: Boost up clock terminal with heuristic approach for NoC E Sakthivel, V Malathi, M Arunraja Journal of Circuits, Systems and Computers 27 (06), 1850084, 2018 | 1 | 2018 |
| Design of optimised logic interface for network‐on‐chip architectures E Sakthivel, M Arunraja, KD Uma, T Shanthi, A Muthukrishnan Electronics Letters 54 (12), 744-746, 2018 | 1 | 2018 |
| FSM Based DFS Link for Network on Chip E Sakthivel, V Malathi, M Arunraja, G Perumalvignesh Circuits and Systems 7 (8), 1734-1750, 2016 | | 2016 |
| Extended Application Algorithm Link Power Reduction in Real Time Bio Network on Chip E Sakthivel, V Malathi, M Arunraja, S Tamilselvi, S Vijayarajan Asian Journal of Research in Social Sciences and Humanities 6 (8), 2285-2299, 2016 | | 2016 |
| CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector E Sakthivel, K Pounraj, V Malathi, M Arunraja, G Perumalvignnesh Circuits and Systems 7 (08), 1760, 2016 | | 2016 |
| Design of Optimized Logic Interface (OLI) for Network on Chip architectures E Sakthivel, M Arunraja, KD Uma, T Shanthi eye 5 (6), 4, 0 | | |
