Kamakoti Veezhinathan
Kamakoti Veezhinathan
Professor, Department of Computer Science, IIT Madras
Verified email at cse.iitm.ac.in - Homepage
Title
Cited by
Cited by
Year
Constructing online testable circuits using reversible logic
SN Mahammad, K Veezhinathan
IEEE transactions on instrumentation and measurement 59 (1), 101-109, 2009
1752009
Efficient building blocks for reversible sequential circuit design
SKS Hari, S Shroff, SN Mahammad, V Kamakoti
2006 49th IEEE International Midwest Symposium on Circuits and Systems 1†…, 2006
882006
A bus encoding technique for power and cross-talk minimization
P Subrahmanya, R Manimegalai, V Kamakoti, M Mutyam
17th International Conference on VLSI Design. Proceedings., 443-448, 2004
512004
LFSR based stream ciphers are vulnerable to power attacks
S Burman, D Mukhopadhyay, K Veezhinathan
International Conference on Cryptology in India, 384-392, 2007
492007
Glitch-aware pattern generation and optimization framework for power-safe scan test
VR Devanathan, CP Ravikumar, V Kamakoti
25th IEEE VLSI Test Symposium (VTS'07), 167-172, 2007
442007
Dynamic coding technique for low-power data bus
M Madhu, VS Murty, V Kamakoti
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 252-253, 2003
422003
System-on-programmable-chip implementation for on-line face recognition
AP Kumar, V Kamakoti, S Das
Pattern Recognition Letters 28 (3), 342-349, 2007
362007
Ultra folded high-speed architectures for Reed Solomon decoders
K Seth, KN Viswajith, S Srinivasan, V Kamakoti
19th International Conference on VLSI Design held jointly with 5th†…, 2006
362006
On power-profiling and pattern generation for power-safe scan tests
VR Devanathan, CP Ravikumar, V Kamakoti
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
352007
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
VR Devanathan, CP Ravikumar, V Kamakoti
2007 IEEE International Test Conference, 1-10, 2007
312007
The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency
A Gautham, K Korgaonkar, P Slpsk, S Balachandran, K Veezhinathan
Presented as part of the 2012 Workshop on Power-Aware Computing and Systems, 2012
302012
PMScan: A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test
VR Devanathan, CP Ravikumar, R Mehrotra, V Kamakoti
2007 IEEE International Test Conference, 1-9, 2007
272007
Detecting SEU-caused routing errors in SRAM-based FPGAs
ESS Reddy, V Chandrasekhar, M SashikŠnth, V Kamakoti, ...
18th International Conference on VLSI Design held jointly with 4th†…, 2005
262005
Face recognition using weighted modular principle component analysis
AP Kumar, S Das, V Kamakoti
International Conference on Neural Information Processing, 362-367, 2004
262004
Shakti-T: A RISC-V processor with light weight security extensions
A Menon, S Murugan, C Rebeiro, N Gala, K Veezhinathan
Proceedings of the Hardware and Architectural Support for Security and†…, 2017
252017
Power virus generation using behavioral models of circuits
K Najeeb, V Vardhan, R Konda, S Kumar, S Hari, V Kamakoti, VM Vedula
25th IEEE VLSI Test Symposium (VTS'07), 35-42, 2007
252007
Reducing SoC test time and test power in hierarchical scan test: Scan architecture and algorithms
VR Devanathan, CP Ravikumar, V Kamakoti
20th International Conference on VLSI Design held jointly with 6th†…, 2007
232007
Automatic constraint based test generation for behavioral HDL models
SKS Hari, VVR Konda, V Kamakoti, VM Vedula, KS Maneperambil
IEEE transactions on very large scale integration (VLSI) systems 16 (4), 408-421, 2008
202008
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs
ES Sundar, V Chandrasekhar, M SashikŠnth, V Kamakoti, V Narayanan
Proceedings. 2004 IEEE International Conference on Field-Programmable†…, 2004
202004
Efficient motion vector recovery algorithm for H. 264 using B-spline approximation
K Seth, V Kamakoti, S Srinivasan
IEEE transactions on broadcasting 56 (4), 467-480, 2010
192010
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