| DSP design protection in CE through algorithmic transformation based structural obfuscation A Sengupta, D Roy, SP Mohanty, P Corcoran IEEE Transactions on Consumer Electronics 63 (4), 467-476, 2017 | 53 | 2017 |
| Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis A Sengupta, D Roy IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems …, 2017 | 32 | 2017 |
| Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters] A Sengupta, D Roy IEEE Consumer Electronics Magazine 6 (2), 118-124, 2017 | 31 | 2017 |
| Protecting IP core during architectural synthesis using HLT-based obfuscation D Roy, A Sengupta Electronics Letters 53 (13), 849-851, 2017 | 26 | 2017 |
| Low cost functional obfuscation of reusable IP cores used in CE hardware through robust locking A Sengupta, D Kachave, D Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 25 | 2018 |
| Low-cost obfuscated JPEG CODEC IP core for secure CE hardware A Sengupta, D Roy, SP Mohanty, P Corcoran IEEE Transactions on Consumer Electronics 64 (3), 365-374, 2018 | 24 | 2018 |
| Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis D Roy, A Sengupta Future Generation Computer Systems 71, 89–101, 2017 | 19 | 2017 |
| Intellectual property-based lossless image compression for camera systems [hardware matters] A Sengupta, D Roy IEEE Consumer Electronics Magazine 7 (1), 119-124, 2017 | 8 | 2017 |
| Enhancing Saliency of an Object using Genetic Algorithm R Pal, D Roy 14th Conference on Computer and Robot Vision, Edmonton, Canada, 2017 | 6 | 2017 |
| Mathematical validation of HWT based lossless image compression A Sengupta, D Roy 2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017 | 5 | 2017 |
| A framework for hardware efficient reusable IP core for grayscale image CODEC A Sengupta, D Roy, SP Mohanty, P Corcoran IEEE Access 6, 871-882, 2017 | 5 | 2017 |
| Reusable intellectual property core protection for both buyer and seller A Sengupta, D Roy Consumer Electronics (ICCE), 2018 IEEE International Conference on, 1-3, 2018 | 4 | 2018 |
| Low cost optimized Trojan secured schedule at behavioral level for single and Nested loop control data flow graphs A Sengupta, D Roy, S Bhadauria Integration, the VLSI Journal, 2016 | 4 | 2016 |
| Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters] D Roy, A Sengupta IEEE Consumer Electronics Magazine 8 (2), 100-102, 2019 | 3 | 2019 |
| Signature-free watermark for protecting digital signal processing cores used in CE devices [hardware matters] P Sarkar, D Roy, A Sengupta, MK Naskar IEEE Consumer Electronics Magazine 8 (1), 92-94, 2018 | 3 | 2018 |
| Low-overhead robust RTL signature for DSP core protection: new paradigm for smart CE design A Sengupta, D Roy, SP Mohanty 2019 IEEE International Conference on Consumer Electronics (ICCE), 1-6, 2019 | 2 | 2019 |
| Multi-phase watermark for IP core protection A Sengupta, D Roy Consumer Electronics (ICCE), 2018 IEEE International Conference on, 1-3, 2018 | 2 | 2018 |
| Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools A Sengupta, D Roy Advances in Engineering Software, 2017 | 2 | 2017 |
| Impact of hardware steganography on DSP core datapath A Sengupta, D Roy CSI Transactions on ICT 7, 137-140, 2019 | 1 | 2019 |
| Low cost dual-phase watermark for protecting CE devices in IoT framework A Sengupta, D Roy Security and Fault Tolerance in Internet of Things, 21-41, 2019 | 1 | 2019 |
Prof. Anirban Sengupta, Fellow IET, Fe...Full Professor, CSE, Indian Institute of Technology (IIT) IndoreVerified email at iiti.ac.in
