Chandan Karfa
Title
Cited by
Cited by
Year
An equivalence-checking method for scheduling verification in high-level synthesis
C Karfa, D Sarkar, C Mandal, P Kumar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
672008
Verification of code motion techniques using value propagation
K Banerjee, C Karfa, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
532014
A formal verification method of scheduling in high-level synthesis
C Karfa, C Mandal, D Sarkar, SR Pentakota, C Reade
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-78, 2006
492006
Formal verification of code motion techniques using data-flow-driven equivalence checking
C Karfa, C Mandal, D Sarkar
ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3 …, 2012
432012
Verification of loop and arithmetic transformations of array-intensive behaviors
C Karfa, K Banerjee, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
232013
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
C Karfa, D Sarkar, C Mandal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
222010
A value propagation based equivalence checking method for verification of code motion techniques
K Banerjee, C Karfa, D Sarkar, C Mandal
2012 International Symposium on Electronic System Design (ISED), 67-71, 2012
122012
Equivalence checking of array-intensive programs
C Karfa, K Banerjee, D Sarkar, C Mandal
2011 IEEE Computer Society Annual Symposium on VLSI, 156-161, 2011
102011
Translation validation of code motion transformations involving loops
R Chouksey, C Karfa, P Bhaduri
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
82018
Translation validation of loop invariant code optimizations involving false computations
R Chouksey, C Karfa, P Bhaduri
International Symposium on VLSI Design and Test, 767-778, 2017
62017
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis
R Chouksey, C Karfa
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (7 …, 2020
42020
Hand-in-hand verification of high-level synthesis
C Karfa, D Sarkar, C Mandal, C Reade
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 429-434, 2007
42007
Sast: An interconnection aware high-level synthesis tool
C Karfa, J Reddy, CR Mandal, D Sarkar, S Biswas
Proc. 9th VLSI Design and Test Symposium, Bangalore, 285-292, 2005
42005
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking
B Tan, R Karri, N Limaye, A Sengupta, O Sinanoglu, MM Rahman, ...
arXiv preprint arXiv:2006.06806, 2020
32020
Experimentation with SMT solvers and theorem provers for verification of loop and arithmetic transformations
C Karfa, K Banerjee, D Sarkar, C Mandal
Proceedings of the 5th IBM Collaborative Academia Research Exchange Workshop …, 2013
32013
Is register transfer level locking secure?
C Karfa, R Chouksey, C Pilato, S Garg, R Karri
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 550-555, 2020
22020
Improving performance of a path-based equivalence checker using counter-examples
R Chouksey, C Karfa, P Bhaduri
2019 32nd International Conference on VLSI Design and 2019 18th …, 2019
22019
Automatic detection of inverse operations while avoiding loop unrolling
K Banerjee, R Chouksey, C Karfa, P Kalita
Proceedings of the 40th International Conference on Software Engineering …, 2018
22018
xMAS based accurate modeling and progress verification of NoCs
S Das, C Karfa, S Biswas
International Symposium on VLSI Design and Test, 792-804, 2017
22017
Verification of KPN level transformations
C Karfa, D Sarkar, C Mandal
2013 26th International Conference on VLSI Design and 2013 12th …, 2013
22013
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