| Novel 4F2 Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device S Verma, S Kaundal, BK Kaushik IEEE Transactions on Nanotechnology 13 (6), 1163-1171, 2014 | 13 | 2014 |
| Next generation spin torque memories BK Kaushik, S Verma, AA Kulkarni, S Prajapati Springer, 2017 | 8 | 2017 |
| Modeling of in-plane magnetic tunnel junction for mixed mode simulations S Verma, S Kaundal, BK Kaushik IEEE Transactions on Magnetics 50 (8), 1-7, 2014 | 7 | 2014 |
| Spintronics-Based Devices to Circuits: Perspectives and challenges. S Verma, AA Kulkarni, BK Kaushik IEEE Nanotechnology Magazine 10 (4), 13-28, 2016 | 6 | 2016 |
| Low-power high-density STT MRAMs on a 3-D vertical silicon nanowire platform S Verma, BK Kaushik IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015 | 6 | 2015 |
| Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based-Qubit Architecture A Kulkarni, S Prajapati, S Verma, BK Kaushik IEEE Transactions on Magnetics 54 (10), 1-9, 2018 | 4 | 2018 |
| Spin Transfer Torque (STT) Based Devices, Circuits, and Memory SV Brajesh Kumar Kaushik ARTECH HOUSE 1, 302, 2016 | 4 | 2016 |
| All spin logic: A micromagnetic perspective S Verma, MS Murthy, BK Kaushik IEEE Transactions on Magnetics 51 (10), 1-10, 2015 | 4 | 2015 |
| Performance Enhancement of STT MRAM Using Asymmetric-Sidewall-Spacer NMOS S Verma, PK Pal, S Mahawar, BK Kaushik IEEE Transactions on Electron Devices 63 (7), 2771-2776, 2016 | 2 | 2016 |
| Next Generation 3-D Spin Transfer Torque Magneto-resistive Random Access Memories BK Kaushik, S Verma, AA Kulkarni, S Prajapati Next Generation Spin Torque Memories, 13-34, 2017 | 1 | 2017 |
| Magnetic Domain Wall Race Track Memory BK Kaushik, S Verma, AA Kulkarni, S Prajapati Next Generation Spin Torque Memories, 71-92, 2017 | 1 | 2017 |
| Low power STT MRAM cell with asymmetric drive current vertical GAA select device S Verma, S Mahawar, BK Kaushik 2015 12th International Conference on Electrical Engineering/Electronics …, 2015 | 1 | 2015 |
| Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell S Prajapati, S Verma, AA Kulkarni, BK Kaushik IEEE Transactions on Nanotechnology 18, 1005-1014, 2018 | | 2018 |
| Spin Orbit Torque MRAM BK Kaushik, S Verma, AA Kulkarni, S Prajapati Next Generation Spin Torque Memories, 35-50, 2017 | | 2017 |
| Multilevel Cell MRAMs BK Kaushik, S Verma, AA Kulkarni, S Prajapati Next Generation Spin Torque Memories, 51-70, 2017 | | 2017 |
| Emerging Memory Technologies BK Kaushik, S Verma, AA Kulkarni, S Prajapati Next Generation Spin Torque Memories, 1-12, 2017 | | 2017 |
| Novel compact model for multi-level spin torque magnetic tunnel junctions S Prajapati, S Verma, AA Kulkarni, BK Kaushik Spintronics IX 9931, 99310I, 2016 | | 2016 |
| Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS S Mahawar, S Verma, PK Pal, BK Kaushik 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | | 2015 |
| Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design PK Pal, S Verma, BK Kaushik, S Dasgupta 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | | 2015 |
| Design of synchronous sequential circuits with low standby sub-threshold leakage-power using back gate bias and testability logic S Verma, RR Pandey 2012 1st International Conference on Emerging Technology Trends in …, 2012 | | 2012 |
Brajesh Kumar KaushikAssociate Professor of Electronics and Communication Engg., IIT-RoorkeeVerified email at iitr.ac.in
