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Dr. Shivam Verma
Dr. Shivam Verma
Department of Electronics Engineering, IIT BHU
Verified email at iitbhu.ac.in - Homepage
Title
Cited by
Cited by
Year
Next generation spin torque memories
BK Kaushik, S Verma, AA Kulkarni, S Prajapati
Springer, 2017
222017
Novel 4F2 Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device
S Verma, S Kaundal, BK Kaushik
IEEE Transactions on Nanotechnology 13 (6), 1163-1171, 2014
172014
Spintronics-based devices to circuits: Perspectives and challenges.
S Verma, AA Kulkarni, BK Kaushik
IEEE Nanotechnology Magazine 10 (4), 13-28, 2016
162016
Spin Transfer Torque (STT) Based Devices, Circuits, and Memory
SV Brajesh Kumar Kaushik
ARTECH HOUSE 1, 302, 2016
92016
Low-power high-density STT MRAMs on a 3-D vertical silicon nanowire platform
S Verma, BK Kaushik
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015
92015
Modeling of a magnetic tunnel junction for a multilevel STT-MRAM cell
S Prajapati, S Verma, AA Kulkarni, BK Kaushik
IEEE Transactions on Nanotechnology 18, 1005-1014, 2018
72018
All spin logic: A micromagnetic perspective
S Verma, MS Murthy, BK Kaushik
IEEE Transactions on Magnetics 51 (10), 1-10, 2015
72015
Modeling of in-plane magnetic tunnel junction for mixed mode simulations
S Verma, S Kaundal, BK Kaushik
IEEE Transactions on Magnetics 50 (8), 1-7, 2014
72014
Optimal Boolean Logic Quantum Circuit Decomposition for Spin-Torque-Based-Qubit Architecture
A Kulkarni, S Prajapati, S Verma, BK Kaushik
IEEE Transactions on Magnetics 54 (10), 1-9, 2018
52018
Performance Enhancement of STT MRAM Using Asymmetric-Sidewall-Spacer NMOS
S Verma, PK Pal, S Mahawar, BK Kaushik
IEEE Transactions on Electron Devices 63 (7), 2771-2776, 2016
42016
Low power STT MRAM cell with asymmetric drive current vertical GAA select device
S Verma, S Mahawar, BK Kaushik
2015 12th International Conference on Electrical Engineering/Electronics …, 2015
32015
Next generation 3-D spin transfer torque magneto-resistive random access memories
BK Kaushik, S Verma, AA Kulkarni, S Prajapati
Next Generation Spin Torque Memories, 13-34, 2017
22017
Magnetic Domain Wall Race Track Memory
BK Kaushik, S Verma, AA Kulkarni, S Prajapati
Next Generation Spin Torque Memories, 71-92, 2017
22017
Novel compact model for multi-level spin torque magnetic tunnel junctions
S Prajapati, S Verma, AA Kulkarni, BK Kaushik
Spintronics IX 9931, 84-92, 2016
22016
Highly reliable STT MRAM using fully depleted body and buried 4H-SiC NMOS
S Mahawar, S Verma, PK Pal, BK Kaushik
2015 IEEE International Conference on Electron Devices and Solid-State …, 2015
12015
Non-Volatile Latch Compatible With Static and Dynamic CMOS for Logic in Memory Applications
S Verma, R Paul, M Shukla
IEEE Transactions on Magnetics 58 (4), 1-8, 2022
2022
Multilayer Micromagnetic Models for All Spin Logic
S Verma
2020 IEEE 17th India Council International Conference (INDICON), 1-5, 2020
2020
Novel Hybrid MTJ-CMOS Based Programmable Gain Amplifier for Portable Applications
S Verma
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020
2020
Next generation 3-D spin transfer torque magneto-resistive random access memories
B Kumar Kaushik, S Verma, AA Kulkarni, S Prajapati
SpringerBriefs in Applied Sciences and Technology, 2017
2017
Magnetic domain wall race track memory
B Kumar Kaushik, S Verma, AA Kulkarni, S Prajapati
SpringerBriefs in Applied Sciences and Technology, 2017
2017
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