| Discrete-time framework for analysis and design of digitally current-mode-controlled intermediate bus architectures for fast transient and stability R Roy, S Kapat IEEE Journal of Emerging and Selected Topics in Power Electronics 8 (4 …, 2020 | 14 | 2020 |
| Input Filter-based Ripple Injection for Mitigating Limit Cycling in Buck Converters Driving CPL R Roy, S Kapat IEEE Journal of Emerging and Selected Topics in Power Electronics, 2020 | 7 | 2020 |
| Automatic speed control of single phase induction motor with the variation of ambient temperature R Roy, S Das, JK Ray, S Barat, B Neogi International Journal of Scientific and Research Publications 2 (11), 2250-3153, 2012 | 7 | 2012 |
| Ripple voltage injection to mitigate limit cycle in digitally controlled intermediate bus architectures R Roy, VI Kumar, S Kapat IEEE Transactions on Power Electronics 35 (3), 3127-3138, 2019 | 5 | 2019 |
| Near time optimal recovery in a digitally current mode controlled buck converter driving a CPL R Roy, S Kapat 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 304-310, 2018 | 3 | 2018 |
| Stabilizing DPWM current mode cascaded DC-DC converters in DC nano-grid without clock sharing R Roy, S Kapat 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), 778-782, 2021 | 1 | 2021 |
| Control and Design Methods to Mitigate Limit Cycle and Improve Performance in Intermediate Bus Architectures R Roy IIT Kharagpur, 2020 | | 2020 |
Santanu KapatProfessor at Indian Institute of Technology (IIT) KharagpurVerified email at ee.iitkgp.ac.in
