| Area–delay–power efficient carry-select adder BK Mohanty, SK Patel IEEE transactions on circuits and systems II: express briefs 61 (6), 418-422, 2014 | 191 | 2014 |
| Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data PK Meher, BK Mohanty, SK Patel, S Ganguly, T Srikanthan IEEE Transactions on Circuits and Systems I: Regular Papers 62 (12), 2836-2845, 2015 | 41 | 2015 |
| LUT optimization for distributed arithmetic-based block least mean square adaptive filter BK Mohanty, PK Meher, SK Patel IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2016 | 35 | 2016 |
| LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing B Garg, SK Patel, S Dutt Electronic Testing, 2020 | 23 | 2020 |
| Reconfigurable Rounding Based Approximate Multiplier for Energy Efficient Multimedia Applications B Garg, S Patel Wireless Personal Communications 118 (2), 919-931, 2021 | 15 | 2021 |
| Area-delay efficient and low-power carry skip adder for high performance computing systems S Patel, B Garg, A Mahajan, S Rai 2019 IEEE International Symposium on Smart Electronic Systems (iSES …, 2019 | 12 | 2019 |
| Area-Delay and Energy Efficient Multi-operand Binary Tree Adder S Patel, S Singhal IET Circuits, Devices & Systems, 2020 | 10 | 2020 |
| Efficient very large-scale integration architecture for variable length block least mean square adaptive filter BK Mohanty, SK Patel IET Signal Processing 9 (8), 605-610, 2015 | 9 | 2015 |
| Reconfigurable carry look-ahead adder trading accuracy for energy efficiency B Garg, SK Patel Journal of Signal Processing Systems 93, 99-111, 2021 | 8 | 2021 |
| An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic SK Patel, B Garg, SK Rai Journal of Electronic Testing, 135–142, 2020 | 6 | 2020 |
| A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth SK RAI, R PANDEY, B GARG, SK PATEL Turkish Journal of Electrical Engineering & Computer Sciences 2020, 2020 | 5 | 2020 |
| Efficient Diminished-1 Modulo (2n +1) Adder using Parallel Prefix Adder SK Singhal, BK Mohanty, SK Patel, G Saxena Journal of Circuits, Systems and Computers, 2019 | 5 | 2019 |
| Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry KA Rao, A Kumar, D Kaplun, SK Patel, N Purohit IET Circuits, Devices & Systems 17 (1), 29-37, 2023 | 2 | 2023 |
| An Automation Methodology for Amelioration of SpyGlassCDC Abstract View Generation Process P Sharma, SK Patel 2021 6th International Conference for Convergence in Technology (I2CT), 1-5, 2021 | 2 | 2021 |
| An area-delay efficient single-precision floating-point multiplier for VLSI systems Anuradha, SK Patel, SK Singhal Microprocessors and Microsystems, 104798, 2023 | 1 | 2023 |
| Area-delay efficient Radix-4 8× 8 Booth multiplier for DSP applications S Singhal, S Patel, A Mahajan, G Saxena Turkish Journal of Electrical Engineering and Computer Sciences 29 (4), 2012 …, 2021 | 1 | 2021 |
| A power and area efficient approximate carry skip adder for error resilient applications SK PATEL, G Bharat, SK RAI Turkish Journal of Electrical Engineering & Computer Sciences 2019 28 (1 …, 2020 | 1 | 2020 |
| Design of Frequency Sampling Rational Rate Polyphase FIR Converter KA Rao, A Kumar, SK Patel, D Kaplun, N Purohit IEEE Transactions on Circuits and Systems II: Express Briefs, .., 2023 | | 2023 |
| Single Image Haze Removal Algorithm with Upgraded Transmission Map Model SK Patel, SK Singhal | | 2023 |
Bharat GargAssistant Professor, Thapar Institute of Engineering & Technology, Deemed University Patiala, PunjabVerified email at thapar.edu
