Zehan Cui (崔泽汉)
Zehan Cui (崔泽汉)
Higon IC Design Co. Ltd.
Verified email at higon.com
Title
Cited by
Cited by
Year
A software memory partition approach for eliminating bank-level interference in multicore systems
L Liu, Z Cui, M Xing, Y Bao, M Chen, C Wu
2012 21st International Conference on Parallel Architectures and Compilation …, 2012
2122012
Going vertical in memory management: Handling multiplicity by multi-policy
L Liu, Y Li, Z Cui, Y Bao, M Chen, C Wu
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
392014
CMD: Classification-based memory deduplication through page access characteristics
L Chen, Z Wei, Z Cui, M Chen, H Pan, Y Bao
ACM SIGPLAN Notices 49 (7), 65-76, 2014
392014
DTail: a flexible approach to DRAM refresh management
Z Cui, SA McKee, Z Zha, Y Bao, M Chen
Proceedings of the 28th ACM international conference on Supercomputing, 43-52, 2014
312014
A fine-grained component-level power measurement method
Z Cui, Y Zhu, Y Bao, M Chen
2011 International Green Computing Conference and Workshops, 1-6, 2011
262011
HaLock: hardware-assisted lock contention detection in multithreaded applications
Y Huang, Z Cui, L Chen, W Zhang, Y Bao, M Chen
Proceedings of the 21st international conference on Parallel architectures …, 2012
252012
BPM/BPM+ Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems
L Liu, Z Cui, Y Li, Y Bao, M Chen, C Wu
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-28, 2014
222014
Message-based memory access apparatus and access method thereof
M Chen, Y Ruan, Z Cui, L Chen, Y Huang, M Chen
US Patent 9,870,327, 2018
212018
MIMS: Towards a message interface based memory system
LC Chen, MY Chen, Y Ruan, YB Huang, ZH Cui, TY Lu, YG Bao
Journal of Computer Science and Technology 29 (2), 255-272, 2014
112014
HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap
Y Huang, L Chen, Z Cui, Y Ruan, Y Bao, M Chen, N Sun
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-25, 2014
112014
Evaluation and optimization of breadth-first search on NUMA cluster
Z Cui, L Chen, M Chen, Y Bao, Y Huang, H Lv
2012 IEEE International Conference on Cluster Computing, 438-448, 2012
72012
A lightweight hybrid hardware/software approach for object-relative memory profiling
L Chen, Z Cui, Y Bao, M Chen, Y Huang, G Tan
2012 IEEE International Symposium on Performance Analysis of Systems …, 2012
72012
Twin-load: Bridging the gap between conventional direct-attached and buffer-on-board memory systems
Z Cui, T Lu, SA McKee, M Chen, H Pan, Y Ruan
Proceedings of the Second International Symposium on Memory Systems, 164-176, 2016
42016
Scattered superpage: A case for bridging the gap between superpage and page coloring
L Chen, Y Wang, Z Cui, Y Huang, Y Bao, M Chen
2013 IEEE 31st International Conference on Computer Design (ICCD), 177-184, 2013
42013
A study of leveraging memory level parallelism for dram system on multi-core/many-core architecture
L Chen, Y Huang, Y Bao, G Tan, Z Cui, M Chen
2013 12th IEEE International Conference on Trust, Security and Privacy in …, 2013
42013
Memory management and device
Y Liu, Y Huang, M Chen, Z Cui, L Chen, Y Ruan
US Patent 10,552,337, 2020
32020
Cracking Intel Sandy Bridge's Cache Hash Function
Z Wei, Z Cui, M Chen
arXiv preprint arXiv:1508.03767, 2015
32015
A swap-based cache set index scheme to leverage both superpage and page coloring optimizations
Z Cui, L Chen, Y Bao, M Chen
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
22014
Method for accessing extended memory, device, and system
Z Cui, M Chen, Y Liu, Y Ruan
US Patent 10,545,672, 2020
12020
Method and apparatus for computer memory management by monitoring frequency of process access
Z Cui, M Chen, L Chen, M Chen
US Patent 9,846,626, 2017
12017
The system can't perform the operation now. Try again later.
Articles 1–20