| Detailed investigation of geometrical factor for pseudo-MOS transistor technique K Komiya, N Bresson, S Sato, S Cristoloveanu, Y Omura IEEE Transactions on Electron Devices 52 (3), 406-412, 2005 | 29 | 2005 |
| Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs A Kawamoto, S Sato, Y Omura IEEE Transactions on electron devices 51 (6), 907-913, 2004 | 27 | 2004 |
| Quantum-mechanical suppression and enhancement of SCEs in ultrathin SOI MOSFETs Y Omura, H Konishi, S Sato IEEE Transactions on Electron Devices 53 (4), 677-684, 2006 | 25 | 2006 |
| Possible influence of the Schottky contacts on the characteristics of ultrathin SOI pseudo-MOS transistors S Sato, K Komiya, N Bresson, Y Omura, S Cristoloveanu IEEE Transactions on Electron Devices 52 (8), 1807-1814, 2005 | 13 | 2005 |
| Roles of chemical stoichiometry and hot electrons in realizing the stable resistive transition of sputter-deposited silicon oxide films R Yamaguchi, S Sato, Y Omura Japanese Journal of Applied Physics 56 (4), 041301, 2017 | 12 | 2017 |
| Sharp switching, hysteresis-free characteristics of Z2-FET for fast logic applications KH Lee, H El Dirani, P Fonteneau, M Bawedin, S Sato, S Cristoloveanu 2018 48th European Solid-State Device Research Conference (ESSDERC), 74-77, 2018 | 10 | 2018 |
| Study on the Impacts of Hole Injection and Inclusion of Sub-Oxide and Metallic Si Atoms on Repeatable Resistance Switching of Sputter-Deposited Silicon Oxide Films Y Omura, R Yamaguchi, S Sato IEEE Transactions on Device and Materials Reliability 18 (4), 561-567, 2017 | 10 | 2017 |
| Revisiting the role of trap-assisted-tunneling process on current-voltage characteristics in tunnel field-effect transistors Y Omura, Y Mori, S Sato, A Mallik Journal of Applied Physics 123 (16), 2018 | 8 | 2018 |
| Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET S Sato, G Ghibaudo, L Benea, I Ionica, Y Omura, S Cristoloveanu Solid-State Electronics 159, 197-203, 2019 | 6 | 2019 |
| On the definition of threshold voltage for tunnel FETs Y Mori, S Sato, Y Omura, A Chattopadhyay, A Mallik Superlattices and Microstructures 107, 17-27, 2017 | 6 | 2017 |
| Proposal of Physics-Based Equivalent Circuit of Pseudo-MOS Capacitor Structure for Impedance Spectroscopy I Yarita, S Sato, Y Omura IEEE Journal of the Electron Devices Society 4 (4), 169-173, 2016 | 6 | 2016 |
| Possible theoretical models for carrier diffusion coefficient of one-dimensional Si wire devices S Sato, Y Omura Japanese Journal of Applied Physics 54 (5), 054001, 2015 | 5 | 2015 |
| Characterization and modeling of resistive-transition phenomena and electronic structure of sputter-deposition SiO2 films R Yamaguchi, S Sato, Y Omura, K Nakamura 2014 11th International Workshop on Low Temperature Electronics (WOLTE), 69-72, 2014 | 5 | 2014 |
| Impact of high-k plug on self-heating effects of SOI MOSFETs K Komiya, T Kawamoto, S Sato, Y Omura IEEE Transactions on Electron Devices 51 (12), 2249-2251, 2004 | 5 | 2004 |
| Possible Models of Electron-Energy Transfer in Resistance Switching by Sputter-Deposited Silicon Oxide Films: Potential of Extremely Low-Energy Switching Y Omura, T Akano, S Sato ECS Journal of Solid State Science and Technology 7 (3), Q21, 2018 | 4 | 2018 |
| Theoretical models for low-frequency noise behaviors of buried-channel MOSFETs Y Omura, S Sato 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2017 | 4 | 2017 |
| Analysis of soft failures in low-resistance interconnect vias using doubly nesting arrays H Shinkawata, S Sato, A Tsuda, T Yoshizawa, T Ohno IEEE Transactions on Semiconductor Manufacturing 27 (2), 178-183, 2014 | 4 | 2014 |
| Origin of transient gate current observed in pseudo-MOS transistor S Sato, T Nguyen, S Cristoloveanu, Y Omura ECS Transactions 6 (4), 95, 2007 | 4 | 2007 |
| Physics-based determination of carrier effective mass assumed in density gradient model S Sato, Y Omura Japanese journal of applied physics 45 (2R), 689, 2006 | 4 | 2006 |
| Detailing Influence of Contact Condition and Island Edge on Dual-Configuration Kelvin Pseudo-MOSFET Method D Mori, I Nakata, M Matsuda, S Sato IEEE Transactions on Electron Devices 68 (6), 2906-2911, 2021 | 3 | 2021 |
