| Implementation of power efficient vedic multiplier N Kayalvizhi International Journal of Computer Applications 43 (16), 21-24, 2012 | 23 | 2012 |
| Power aware and high speed reconfigurable modified booth multiplier SS Sakthi, N Kayalvizhi 2011 IEEE Recent Advances in Intelligent Computational Systems, 352-356, 2011 | 12 | 2011 |
| Measurement of pulse transit time (PTT) using photoplethysmography M Lokharan, KCL Kumar, VH Kumar, N Kayalvizhi, R Aryalekshmi The 16th International Conference on Biomedical Engineering, 130-134, 2017 | 11 | 2017 |
| Generation of new march tests with low test power and high fault coverage by test sequence reordering using genetic algorithm CV Gayathri, N Kayalvizhi, M Mallikadevi 2009 International Conference on Advances in Recent Technologies in …, 2009 | 9 | 2009 |
| Estimating correlation between arterial blood pressure and photoplethysmograph T Abhay, N Kayalvizhi The 16th International Conference on Biomedical Engineering, 47-52, 2017 | 3 | 2017 |
| High throughput multipliers using delay equalization A Raj, N Kayalvizhi International Journal of Computer Applications 2 (4), 9-13, 2010 | 2 | 2010 |
| Age Dependence of Pulse Transit Time Derived from dual PPGs and PPG-ECG duo‐A comparative Study L Mukundan, N Kayalvizhi 2017 14th IEEE India Council International Conference (INDICON), 1-4, 2017 | 1 | 2017 |
| Power Aware Reconfigurable Multiplier for DSP Applications SS Sakthi, N Kayalvizhi International Journal of Computer Science and Engineering Technology (IJCSET), 2011 | 1 | 2011 |
| Correlation of PPG and Accelerometer Signals V Dhanya, N Kayalvizhi 2020 4th International Conference on Electronics, Communication and …, 2020 | | 2020 |
| ECG System as Smartphone Peripheral PS Dey, N Kayalvizhi 2019 9th International Conference on Advances in Computing and Communication …, 2019 | | 2019 |
| A 2.89ppm/°C Current Reference Generation with Temperature Compensation using 90-nm CMOS Circuit NMN Kayalvizhi IJAER 10 (12), 32363-32369, 2015 | | 2015 |
| A 4.2ppm/°C Temperature Compensated CMOS Voltage Reference NK Paulcy Paul IJAER 10 (Number 9), 23739-23746, 2015 | | 2015 |
| COMPARISON OF PARALLEL SUMMATION AND WEAK INVERSION BASED LOGARITHMIC AMPLIFIER NK Amrutha Paul IJRET 3 (12), 2014 | | 2014 |
| Adiabatic Technique for Designing Energy Efficient Logic Circuits S Jahan, N Kayalvizhi International Conference on Eco-friendly Computing and Communication Systems …, 2012 | | 2012 |
| Alka Raj N Kayalvizhi | | 2010 |
| Adarsh S 62 Aditya Lokesh 295 Ahammed Muneer KV 235,116 Akhil PV 97 MB Akshay, AM John, AS Anand, A Brigit, A Joykutty, A Tharakan, S Asha, ... | | |
| 2019 9th International Conference on Advances in Computing and Communication (ICACC) K Sreelakshmi, TT Sasidhar, N Mohan, S Kp, R Ravindran, A Viswakumar, ... | | |
