| Multi-application based network-on-chip design for mesh-of-tree topology using global mapping and reconfigurable architecture M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkeramaddi 2019 32nd international conference on VLSI Design and 2019 18th …, 2019 | 17 | 2019 |
| Patternet: explore and exploit filter patterns for efficient deep neural networks B Khaleghi, U Mallappa, D Yaldiz, H Yang, M Shah, J Kang, T Rosing Proceedings of the 59th ACM/IEEE Design Automation Conference, 223-228, 2022 | 5 | 2022 |
| Fault tolerant routing methodology for mesh-of-tree based network-on-chips using local reconfiguration M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkeramaddi 2018 International Conference on High Performance Computing & Simulation …, 2018 | 3 | 2018 |
| A novel fault-tolerant routing algorithm for mesh-of-tree based network-on-chips M Shah, M Upadhyay, PV Bhanu, J Soumya, LR Cenkeramaddi International Symposium on VLSI Design and Test, 446-459, 2018 | 3 | 2018 |
| A novel fault-tolerant routing technique for mesh-of-tree based network-on-chip design M Upadhyay, M Shah, PV Bhanu, J Soumya, LR Cenkarmaddi, H Idsøe TENCON 2018-2018 IEEE Region 10 Conference, 2378-2383, 2018 | 1 | 2018 |
| Deep Neural Network Operation Via Patterned Filter Clustering and Activation Group Reuse B Khaleghi, J Kang, H XU, J Morris, T Rosing, UBS Mallappa, H Yang, ... US Patent App. 18/441,569, 2024 | | 2024 |
| FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and Hyperdimensional Computing H Yang, CE Song, W Xu, B Khaleghi, U Mallappa, M Shah, K Fan, M Kang, ... 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 33-36, 2024 | | 2024 |
| High-dimensional vector space encoding techniques for hyperdimensional computing systems B Khaleghi, J Kang, H Xu, J Morris, T Rosing, UBS Mallappa, H Yang, ... US Patent App. 18/441,318, 2024 | | 2024 |
Soumya JAssociate Professor at BITS Pilani, Hyderabad CampusVerified email at hyderabad.bits-pilani.ac.in
