| A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS G Balamurugan, J Kennedy, G Banerjee, JE Jaussi, M Mansuri, ... IEEE Journal of Solid-State Circuits 43 (4), 1010-1019, 2008 | 208 | 2008 |
| A 5-GHz 108-Mb/s 22 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm Power Amplifiers in 90-nm CMOS Y Palaskas, A Ravi, S Pellerano, BR Carlton, MA Elmala, R Bishop, ... IEEE Journal of Solid-State Circuits 41 (12), 2746-2756, 2006 | 106 | 2006 |
| Total dose effects on the shallow-trench isolation leakage current characteristics in a 0.35/spl mu/m SiGe BiCMOS technology G Niu, SJ Mathew, G Banerjee, JD Cressler, SD Clark, MJ Palmer, ... IEEE Transactions on Nuclear Science 46 (6), 1841-1847, 1999 | 54 | 1999 |
| Anomalous dose rate effects in gamma irradiated SiGe heterojunction bipolar transistors G Banerjee, G Niu, JD Cressler, SD Clark, MJ Palmer, DC Ahlgren IEEE Transactions on Nuclear Science 46 (6), 1620-1626, 1999 | 53 | 1999 |
| A CMOS gas sensor array platform with Fourier transform based impedance spectroscopy P Murali, K Ranjit, N Bhat, G Banerjee, B Amrutur, KN Bhat, ... IEEE Transactions on Circuits and Systems I: Regular Papers 59 (11), 2507-2517, 2012 | 32 | 2012 |
| A 0.1–3.5-GHz duty-cycle measurement and correction technique in 130-nm CMOS I Raja, G Banerjee, MA Zeidan, JA Abraham IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015 | 28 | 2015 |
| A 0.1–2-GHz quadrature correction loop for digital multiphase clock generation circuits in 130-nm CMOS I Raja, V Khatri, Z Zahir, G Banerjee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3 …, 2016 | 27 | 2016 |
| A 1.4 V, 2.4/5 GHz, 90nm CMOS system in a package transceiver for next generation WLAN A Ravi, BR Carlton, Y Palaskas, G Banerjee, RE Bishop, MA Elmala, ... Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., 294-297, 2005 | 27 | 2005 |
| Signal generator for a built-in self test G Banerjee, M Behera US Patent App. 12/776,168, 2011 | 25 | 2011 |
| Electrical probing of surface and bulk traps in proton-irradiated gate-assisted lateral PNP transistors G Niu, G Banerjee, JD Cressler, JM Roldan, SD Clark, DC Ahlgren IEEE Transactions on Nuclear Science 45 (6), 2361-2365, 1998 | 24 | 1998 |
| A 0.25–3.25-GHz wideband CMOS-RF spectrum sensor for narrowband energy detection V Khatri, G Banerjee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (9 …, 2016 | 23 | 2016 |
| Analog/RF built-in-self-test subsystem for a mobile broadcast video receiver in 65-nm CMOS G Banerjee, M Behera, MA Zeidan, R Chen, K Barnett IEEE journal of solid-state circuits 46 (9), 1998-2008, 2011 | 23 | 2011 |
| A 5GHz 108Mb/s 2x2 MIMO transceiver with fully integrated+ 16dbm PAs in 90nm CMOS Y Palaskas, A Ravi, S Pellerano, BR Carlton, MA Elmala, R Bishop, ... Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical …, 2006 | 21 | 2006 |
| Adaptively extending tunable range of frequency in a closed loop A Ravi, K Soumyanath, G Banerjee US Patent 6,885,873, 2005 | 18 | 2005 |
| Desensitized CMOS low-noise amplifiers G Banerjee, K Soumyanath, DJ Allstot IEEE Transactions on Circuits and Systems I: Regular Papers 55 (3), 752-765, 2008 | 17 | 2008 |
| Differential multi-phase DLL for reconfigurable radio frequency synthesizer JS Gaggatur, V Khatri, I Raja, MK Lenka, G Banerjee 2014 IEEE International Conference on Electronics, Computing and …, 2014 | 16 | 2014 |
| A multi-tap inductor based 2.0–4.1 GHz wideband LC-oscillator Z Zahir, G Banerjee 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 330-333, 2016 | 15 | 2016 |
| A 3.2 mW 0.13 μm high sensitivity frequency-domain CMOS capacitance interface JS Gaggatur, PK Dixena, G Banerjee 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1070-1073, 2016 | 15 | 2016 |
| High gain capacitance sensor interface for the monitoring of cell volume growth JS Gaggatur, G Banerjee 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 14 | 2017 |
| Passive impedance equalization of high speed serial links G Banerjee, S Mooney US Patent App. 11/343,780, 2007 | 14 | 2007 |
Javed S GaggaturTechnical Lead / Manager-High Speed CircuitsVerified email at intel.com
