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Rakhi Narang
Rakhi Narang
University of Delhi
Verified email at ieee.org
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A dielectric-modulated tunnel-FET-based biosensor for label-free detection: Analytical modeling study and sensitivity analysis
R Narang, KVS Reddy, M Saxena, RS Gupta, M Gupta
IEEE transactions on electron devices 59 (10), 2809-2817, 2012
1582012
Comparative analysis of dielectric-modulated FET and TFET-based biosensor
R Narang, M Saxena, M Gupta
IEEE Transactions on Nanotechnology 14 (3), 427-435, 2015
1262015
Dielectric modulated tunnel field-effect transistor—A biomolecule sensor
R Narang, M Saxena, RS Gupta, M Gupta
IEEE Electron Device Letters 33 (2), 266-268, 2011
1162011
Assessment of ambipolar behavior of a tunnel FET and influence of structural modifications
R Narang, M Saxena, RS Gupta, M Gupta
JSTS: Journal of Semiconductor Technology and Science 12 (4), 482-491, 2012
972012
Impact of Temperature variations on the Device and Circuit Performance of Tunnel FET: A Simulation Study
R Narang, M Saxena, RS Gupta, M Gupta
IEEE Transactions on Nanotechnology 12 (6), 951-957, 0
73*
Investigation of dielectric modulated (DM) double gate (DG) junctionless MOSFETs for application as a biosensors
R Narang, M Saxena, M Gupta
Superlattices and Microstructures 85, 557-572, 2015
632015
Drain current model for a gate all around (GAA) p–n–p–n tunnel FET
R Narang, M Saxena, RS Gupta, M Gupta
Microelectronics Journal 44 (6), 479-488, 2013
482013
Analytical model of pH sensing characteristics of junctionless silicon on insulator ISFET
R Narang, M Saxena, M Gupta
IEEE Transactions on Electron Devices 64 (4), 1742-1750, 2017
472017
Device and circuit level performance comparison of tunnel FET architectures and impact of heterogeneous gate dielectric
R Narang, M Saxena, RS Gupta, M Gupta
JSTS: Journal of Semiconductor Technology and Science 13 (3), 224-236, 2013
412013
Modeling and TCAD assessment for gate material and gate dielectric engineered TFET architectures: circuit-level investigation for digital applications
R Narang, M Saxena, M Gupta
IEEE Transactions on Electron Devices 62 (10), 3348-3356, 2015
402015
Modeling and simulation investigation of sensitivity of symmetric split gate junctionless FET for biosensing application
R Narang, M Saxena, M Gupta
IEEE Sensors Journal 17 (15), 4853-4861, 2017
372017
Linearity and analog performance analysis of double gate tunnel FET: effect of temperature and gate stack
R Narang, M Saxena, RS Gupta, M Gupta
International Journal of VLSI Design & Communication Systems 2 (3), 185, 2011
322011
Modeling of gate underlap junctionless double gate MOSFET as bio-sensor
R Narang, M Saxena, M Gupta
Materials Science in Semiconductor Processing 71, 240-251, 2017
242017
Drain current model of a four-gate dielectric modulated MOSFET for application as a biosensor
R Narang, M Saxena, M Gupta
IEEE Transactions on Electron Devices 62 (8), 2636-2644, 2015
242015
Model of GaSb-InAs pin gate all around BioTunnel FET
R Narang, M Saxena, M Gupta
IEEE Sensors Journal 19 (7), 2605-2612, 2018
192018
Model of GaSb-InAs pin gate all around BioTunnel FET
R Narang, M Saxena, M Gupta
IEEE Sensors Journal 19 (7), 2605-2612, 2018
192018
Simulation study for dual material gate hetero-dielectric TFET: Static performance analysis for analog applications
R Narang, M Gupta, M Saxena
2013 Annual IEEE India Conference (INDICON), 1-6, 2013
192013
Modeling and simulation of junctionless double gate radiation sensitive FET (RADFET) dosimeter
A Dubey, A Singh, R Narang, M Saxena, M Gupta
IEEE Transactions on Nanotechnology 17 (1), 49-55, 2017
172017
Exploring the applicability of well optimized dielectric pocket tunnel transistor for future low power applications
R Narang, M Saxena, M Gupta
Superlattices and Microstructures 126, 8-16, 2019
152019
Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules
R Narang, M Saxena, M Gupta
Superlattices and Microstructures 88, 225-243, 2015
142015
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