| Solution to ceed problem using classical approach of lagrange's and pso algorithms M Balaji, G Naresh International Journal of Innovations in Engineering and Technology 4 (4), 13-19, 2014 | 8 | 2014 |
| Low Power Dissipation of 4 bit Parallel adder/subtractor using Dual sleep and ground bounce technique in 120nm and 90nm Technology GN T.Krishna Moorthy, M.Balaji ” International Journal of VLSI and Embedded Systems (IJVES) 4 (10162), 610-614, 2013 | 2* | 2013 |
| Design of Three-Input Floating Point Adder/Subtractor I Ms. A. Niharika, Mr. G. Naresh ,Ms. Neelima K ,Assistant Professor ... International Journal of Engineering Research & Technology (IJERT) 9 (8), 51-53, 2021 | | 2021 |
| DESIGN OF TRANSISTOR LEVEL 4-BIT X 4-BIT FAST MULTIPLIER RUM Ganekanti Naresh Journal of Emerging Technologies and Innovative Research (JETIR) 6 (4), 310-318, 2019 | | 2019 |
| Design and Verification of I2C Protocol by using System Verilog KS G NARESH International Journal of Electronics, Electrical and Computational System 7 …, 2018 | | 2018 |
| Design and Development of a Signal Conditioning Board for Industrial Applications KKS G Naresh,C Venkata Sudhakar International Journal of Trend in Research and Development 4, 404-408, 2017 | | 2017 |
| HIGH SPEED 3TAP FIR FILTER AND ANALYSIS OF PARALLEL SELF TIMED ADDER VS G.Naresh International Journal of Pure and Applied Mathematics 114 (10), 271-277, 2017 | | 2017 |
| Parallel Prefix Adders based Matrix-Vector Multiplier for Iterative Methods in CDMA Communication Systems B Prathyusha, G Naresh i-Manager's Journal on Electronics Engineering 6 (4), 18, 2016 | | 2016 |
| DESIGN OF BRAUN MULTIPLIERS WITH SELF-CHECKING BASED ON TWO-RAIL ENCODING R Rogini, G Naresh | | 2015 |
| Compressor Based Self-Checking Carry-Select Adder Design Based On Two-Rail Encoding GN R.Rogini International Journal Of Research In Computer Applications And Robotics 3 (4 …, 2015 | | 2015 |
| Efficient Diminished-1 Modulo 2n+1 Mac Unit Architecture YSB G.Naresh International Journal Of Research In Computer Applications And Robotics 3 …, 2015 | | 2015 |
| Implementation of Self-Checking Carry-Select Adder Based on Two-Rail Encoding in FPGA G Naresh, PP Kumar | | 2015 |
| Design And Implementation Of Split Radix Algorithm For Length - 6m DFT Using VLSI And FPGA SS G.Naresh International Journal Of Research In Computer Applications And Robotics 2 (7 …, 2014 | | 2014 |
| Optimizing The Gate Level Area In Digit Serial FIR Filter Design With An MCM Blocks GN Bayikati Yagneswar ”, International Journal of Engineering Research and Applications 4 (6), 80-89, 2014 | | 2014 |
| INTERNATIONAL JOURNAL OF RESEARCH IN COMPUTER APPLICATIONS AND ROBOTICS J Singh | | 2014 |
| Lay out Design of 4-bit Ripple Carry Adder Using NOR and NAND Logic GN T.Ravisekhar, K. V.Rajendra Prasad International Journal of VLSI and Embedded Systems 4 (09157), 2013 | | 2013 |
