Janusz Rajski
Janusz Rajski
Vice President of Engineering, Siemens
Verified email at mentor.com
Cited by
Cited by
Embedded deterministic test
J Rajski, J Tyszer, M Kassab, N Mukherjee
IEEE transactions on computer-aided design of integrated circuits and …, 2004
Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
S Hellebrand, J Rajski, S Tarnick, S Venkataraman, B Courtois
IEEE Transactions on Computers 44 (2), 223-233, 1995
Embedded deterministic test for low cost manufacturing test
J Rajski, J Tyszer, M Kassab, N Mukherjee, R Thompson, KH Tsai, ...
Proceedings. International Test Conference, 301-310, 2002
Logic BIST for large industrial designs: Real issues and case studies
G Hetherington, T Fryars, N Tamarapalli, M Kassab, A Hassan, J Rajski
International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.
S Hellebrand, S Tarnick, B Courtois, J Rajski
ITC, 120-129, 1992
Preferred fill: A scalable method to reduce capture power for scan based designs
S Remersaro, X Lin, Z Zhang, SM Reddy, I Pomeranz, J Rajski
2006 IEEE International Test Conference, 1-10, 2006
Testing and diagnosis of interconnects using boundary scan architecture
A Hassan, J Rajski, VK Agarwal
International Test Conference 1988 Proceeding@ m_New Frontiers in Testing …, 1988
Arithmetic built-in self-test for embedded systems
J Rajski, J Tyszer
Prentice-Hall, Inc., 1998
Impact of multiple-detect test patterns on product quality
B Benware, C Schuermyer, S Ranganathan, R Madge, P Krishnamurthy, ...
International Test Conference, 2003. Proceedings. ITC 2003., 1031-1031, 2003
Arithmetic built-in self test of multiple scan-based integrated circuits
J Rajski, J Tyszer
US Patent 5,991,898, 1999
Test pattern compression for an integrated circuit test environment
J Rajski, J Tyszer, M Kassab, N Mukherjee
US Patent 6,327,687, 2001
High-frequency, at-speed scan testing
X Lin, R Press, J Rajski, P Reuter, T Rinderknecht, B Swanson, ...
IEEE Design & Test of Computers 20 (5), 17-25, 2003
A method of fault analysis for test generation and fault diagnosis
H Cox, J Rajski
IEEE transactions on computer-aided design of integrated circuits and …, 1988
Timing-aware ATPG for high quality at-speed testing of small delay defects
X Lin, KH Tsai, C Wang, M Kassab, J Rajski, T Kobayashi, R Klingenberg, ...
2006 15th Asian Test Symposium, 139-146, 2006
Method and apparatus for selectively compacting test responses
J Rajski, J Tyszer, M Kassab, N Mukherjee
US Patent 6,557,129, 2003
Constructive multi-phase test point insertion for scan-based BIST
N Tamarapalli, J Rajski
Proceedings International Test Conference 1996. Test and Design Validity …, 1996
Decompressor/PRPG for applying pseudo-random and deterministic test patterns
J Rajski, J Tyszer, M Kassab, N Mukherjee
US Patent 6,684,358, 2004
Convolutional compaction of test responses
J Rajski, J Tyszer, C Wang, SM Reddy
International Test Conference, 745-754, 2003
Parallel decompressor and related methods and apparatuses
J Rajski, J Tyszer
US Patent 5,991,909, 1999
Test data decompression for multiple scan designs with boundary scan
J Rajski, J Tyszer, N Zacharia
IEEE Transactions on Computers 47 (11), 1188-1200, 1998
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