| YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs P Prasad, K Parane, B Talawar VLSI Design and 2018 17th International Conference on Embedded Systems …, 2018 | 11 | 2018 |
| FPGA based noc simulation acceleration framework supporting adaptive routing K Parane, P Prabhu, B Talawar 2018 IEEE International Conference on Electronics, Computing and …, 2018 | 10 | 2018 |
| LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA K Parane, P Prasad B M, B Talawar ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (1 …, 2020 | 8 | 2020 |
| Design of an adaptive and reliable network on chip router architecture using FPGA K Parane, BMP Prasad, B Talawar 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019 | 7 | 2019 |
| FPGA friendly NoC simulation acceleration framework employing the hard blocks BMP Prasad, K Parane, B Talawar Computing, 1-23, 2021 | 6 | 2021 |
| An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks BM Prabhu Prasad, K Parane, B Talawar Circuits, Systems, and Signal Processing, 1-25, 2020 | 6 | 2020 |
| High-performance NoCs employing the DSP48E1 blocks of the Xilinx FPGAs P Prasad, K Parane, B Talawar 20th international symposium on quality electronic design (ISQED), 163-169, 2019 | 6 | 2019 |
| Trace-driven simulation and design space exploration of network-on-chip topologies on FPGA GS Sangeetha, V Radhakrishnan, P Prasad, K Parane, B Talawar 2018 8th International Symposium on Embedded Computing and System Design …, 2018 | 6 | 2018 |
| High-performance NoC simulation acceleration framework employing the xilinx DSP48E1 blocks BMP Prasad, K Parane, B Talawar 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2019 | 5 | 2019 |
| YaNoC: Yet another network-on-chip simulation acceleration engine supporting congestion-aware adaptive routing using FPGAs K Parane, BM Prabhu Prasad, B Talawar Journal of Circuits, Systems and Computers 28 (12), 1950202, 2019 | 4 | 2019 |
| P-noc: performance evaluation and design space exploration of nocs for chip multiprocessor architecture using fpga K Parane, BM Prabhu Prasad, B Talawar Wireless Personal Communications 114 (4), 3295-3319, 2020 | 3 | 2020 |
| Hy-BTree: An efficient Tree based topology for FPGA based NoC implementation BMP Prasad, K Parane, B Talawar 2021 IEEE International Conference on Electronics, Computing and …, 2021 | 1 | 2021 |
| Analysis of cache behaviour and software optimizations for faster on-chip network simulations BMP Prasad, K Parane, B Talawar International Journal of System Assurance Engineering and Management, 1-17, 2019 | 1 | 2019 |
| Cache analysis and software optimizations for faster on-chip network simulations K Parane, PP B M, B Talawar Industrial and Information Systems (ICIIS), 2016 11th International …, 2018 | 1 | 2018 |
Khyamling ParaneNITKVerified email at nitk.edu.in
