| Performance evaluation of subthreshold Schmitt trigger using body bias techniques M Janveja, A Khan, V Niranjan 2016 International Conference On Computational Techniques In Information And …, 2016 | 12 | 2016 |
| Design and analysis of efficient vedic multiplier for fast computing applications A Verma, A Khan, S Wairya International Journal of Computing and Digital Systems 13 (1), 190-201, 2023 | 6 | 2023 |
| Performance Evaluation of Highly Efficient XOR and XOR-XNOR Topologies using CNTFET for Nanocomputation A Khan, S Wairya International Journal of Computing and Digital System, 225-236, 2021 | 2 | 2021 |
| Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder A Khan, A Chakraborty, UB Joy, S Wairya, M Hasan Microelectronics Journal 140, 105949, 2023 | 1 | 2023 |
| High-performance 3–2 Compressor Using Efficient XOR-XNOR in Nanotechnology A Khan, S Wairya VLSI, Microwave and Wireless Technologies: Select Proceedings of ICVMWT 2021 …, 2022 | 1 | 2022 |
| Performance Evaluation of Master–Slave D Flip Flop Based on Charge Retention Feedback Pass Transistor Logic in Nanotechnology S Tripathi, A Khan, S Wairya Recent Trends in Electronics and Communication: Select Proceedings of VCAS …, 2022 | 1 | 2022 |
| Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design Sana, A Khan, S Wairya International Journal of Innovative Technology and Exploring Engineering …, 2020 | 1 | 2020 |
| Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass Transistor Logic P Gupta, A Khan, S Wairya 2023 4th IEEE Global Conference for Advancement in Technology (GCAT), 1-6, 2023 | | 2023 |
| Performance Analysis of Ternary Full Adder designs using proposed Ternary 3: 1 MUX P Gupta, A Khan, S Wairya 2023 Second International Conference on Trends in Electrical, Electronics …, 2023 | | 2023 |
| Performance Analysis of Vedic Multiplier Using High Performance XOR-MUX Based Adder for Fast Computation A Verma, A Khan, S Wairya Advances in VLSI, Communication, and Signal Processing: Select Proceedings …, 2022 | | 2022 |
| Low-Power Shift Registers Using Fully Static Contention Free Single-Phase Clocked Flip Flop P Tripathi, A Khan, S Wairya Recent Trends in Electronics and Communication: Select Proceedings of VCAS …, 2022 | | 2022 |
| Low-Power High-Performance Hybrid Scalable A Verma, A Khan, S Wairya Proceedings of First International Conference on Computational Electronics …, 2022 | | 2022 |
| An Efficient ALU Architecture Topology for Nanotechnology Applications A Khan, S Wairya 2021 8th International Conference on Signal Processing and Integrated …, 2021 | | 2021 |
| Performance Evaluation of Energy-Efficient Adiabatic Logic Circuit-Based Multiplexer for Low Power Applications S Jaiswal, Prashasti, A Khan, S Wairya Advances in VLSI, Communication, and Signal Processing: Select Proceedings …, 2021 | | 2021 |
| Design and Performance Evaluation of Highly Efficient Adders in Nanometer Technology Prashasti, S Jaiswal, A Khan, S Wairya Advances in VLSI, Communication, and Signal Processing: Select Proceedings …, 2021 | | 2021 |
| High performance and low power D flip-flop using pulsed latch technique SJ Prashasti, A Khan, S Wairya IJAER, ISSN, 0973-4562, 2019 | | 2019 |
| High Performance and Low Power D Flip-Flop using Pulsed Latch S Jaiswal, A Khan, S Wairya | | |
Subodh WairyaProfessor EC Deptt Institute of Engineering & Technology, LucknowVerified email at ietlucknow.ac.in
