| 20mw, 125 msps, 10 bit pipelined adc in 65nm standard digital cmos process PN Singh, A Kumar, C Debnath, R Malik 2007 IEEE Custom Integrated Circuits Conference, 189-192, 2007 | 32 | 2007 |
| Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms JN Tripathi, NK Chhabra, RK Nagpal, R Malik, J Mukherjee 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 361-364, 2012 | 13 | 2012 |
| Signal integrity and power integrity methodology for robust analysis of on-the-board system for high speed serial links RK Nagpal, R Malik, JN Tripathi 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 13 | 2009 |
| Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry A Bhuvanagiri, H Singh, R Malik, N Chawla US Patent 7,698,355, 2010 | 12 | 2010 |
| Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry A Bhuvanagiri, H Singh, R Malik, N Chawla US Patent 7,698,355, 2010 | 12 | 2010 |
| Design of planar ebg structures using cuckoo search algorithm for power/ground noise suppression PR Pani, RK Nagpal, R Malik, N Gupta Progress In Electromagnetics Research M 28, 145-155, 2013 | 11 | 2013 |
| A 1.2 v 11b 100Msps 15mW ADC realized using 2.5 b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process PN Singh, A Kumar, C Debnath, R Malik 2008 IEEE custom integrated circuits conference, 305-308, 2008 | 11 | 2008 |
| Maintaining power integrity by damping the cavity-mode anti-resonances' peaks on a power plane by particle swarm optimization JN Tripathi, RK Nagpal, NK Chhabra, R Malik, J Mukherjee Thirteenth International Symposium on Quality Electronic Design (ISQED), 525-528, 2012 | 10 | 2012 |
| Signal integrity and power integrity issues at system level JN Tripathi, RK Nagpal, R Malik IETE Technical Review 29 (5), 365-371, 2012 | 8 | 2012 |
| Robust optimization and reflection gain enhancement of serial link system for signal integrity and power integrity JN Tripathi, RK Nagpal, R Malik Int. J. of Design, Analysis and Tools for Circuits and Systems 2 (1), 70-85, 2011 | 8 | 2011 |
| Robust optimization of serial link system for signal integrity and power integrity JN Tripathi, RK Nagpal, R Malik 2010 IEEE International Conference on Networked Embedded Systems for …, 2010 | 7 | 2010 |
| Power integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization JN Tripathi, RK Nagpal, NK Chhabra, R Malik, J Mukherjee, PR Apte International Symposium on Quality Electronic Design (ISQED), 670-675, 2013 | 6 | 2013 |
| Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output R Malik, P Goel US Patent 7,007,053, 2006 | 6 | 2006 |
| Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output R Malik, P Goel US Patent 7,007,053, 2006 | 6 | 2006 |
| Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output R Malik, P Goel US Patent 7,007,053, 2006 | 6 | 2006 |
| Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output R Malik, P Goel US Patent 7,007,053, 2006 | 6 | 2006 |
| Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output R Malik, P Goel US Patent 7,007,053, 2006 | 6 | 2006 |
| Device for implementing a sum of products expression A Bhuvanagiri, R Malik, N Chawla US Patent 7,917,569, 2011 | 5 | 2011 |
| Device for implementing a sum of products expression A Bhuvanagiri, R Malik, N Chawla US Patent 7,917,569, 2011 | 5 | 2011 |
| Scheme for improving settling behavior of gain boosted fully differential operational amplifier PN Singh, C Debnath, R Malik, AJ D'souza US Patent 7,737,780, 2010 | 4 | 2010 |
