| 3D (dimensional)—Wired and wireless network-on-chip (NoC) N Ashokkumar, P Nagarajan, P Venkatramana Inventive Communication and Computational Technologies, 113-119, 2020 | 17 | 2020 |
| Fake job detection and analysis using machine learning and deep learning algorithms CS Anita, P Nagarajan, GA Sairam, P Ganesh, G Deepakkumar Revista Geintec-Gestao Inovacao e Tecnologias 11 (2), 642-650, 2021 | 15 | 2021 |
| Low power design methodology V Natarajan, AK Nagarajan, N Pandian, VG Savithri Very-Large-Scale Integration, 47, 2018 | 13 | 2018 |
| Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems P Nagarajan, NA Kumar, PV Ramana International Journal of Wavelets, Multiresolution and Information …, 2020 | 10 | 2020 |
| Design challenges for 3 Dimensional Network-on-Chip (NoC) nagarajan ashok kumar Sustainable communication networks and application, pp773-782, 2019 | 10 | 2019 |
| Hand Gesture Recognition Based Real-time Command System PJ Martina, P Nagarajan, P Karthikeyan IJCSMC 2 (4), 295-299, 2013 | 8 | 2013 |
| Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture P Nagarajan, NA Kumar, JA Dhanraj, TS Kumar 2022 International Conference on Electronics and Renewable Systems (ICEARS …, 2022 | 7 | 2022 |
| Quad-Rail Sense-Amplifier based NoC Router Design NP , Ashok Kumar Nagarajan Data Engineering and Communication Technologies, 1449-1454, 2019 | 7* | 2019 |
| Design of register element for low power clocking system P Nagarajan, R Saravanan, P Thirumurugan Information-An International Interdisciplinary Journal 17 (6), 2903-2913, 2014 | 6 | 2014 |
| Design of Three-valued Logic Half-Subtractor using GNRFET P Venkatramana, P Nagarajan, SJ Basha 2023 International Conference on Recent Advances in Electrical, Electronics …, 2023 | 4 | 2023 |
| FPGA implementation of arbiters algorithm for network-on-chip SSPN T. Kavitha ARPN Journal of Engineering and Applied Sciences 11 (19), 11451-11456, 2017 | 4 | 2017 |
| Design and analysis of double edge triggered clocked latch for low power VLSI applications G Sabadini, PM Kumar, P Nagarajan 2016 10th International Conference on Intelligent Systems and Control (ISCO …, 2016 | 4 | 2016 |
| Efficient timing element design featuring low power VLSI applications P Nagarajan, T Kavitha, S Shiyamala International Journal of Engineering and Technology (IJET), 2016 | 4 | 2016 |
| Bluetooth based garage door opening system CK Pappa, N Ashokkumar, P Nagarajan, K Thandapani 2023 5th International Conference on Smart Systems and Inventive Technology …, 2023 | 3 | 2023 |
| Analysis of Millimeter-Wave based on Multichannel Wireless Networks-on-Chip NA Kumar, P Nagarajan, JA Dhanraj, TS Kumar 2022 International Conference on Electronics and Renewable Systems (ICEARS …, 2022 | 3 | 2022 |
| Design and Analysis of Register Element for Low Power Clocking System P Nagarajan, S R International Journal of Computer Science and Mobile Computing 2 (4), 38-45, 2013 | 3 | 2013 |
| Radio over fiber on gigabit passive optical network using QPSK modulation scheme T Kavitha, A Arulmary, P Nagarajan Journal of Optical Communications 44 (s1), s1023-s1027, 2024 | 2 | 2024 |
| Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture P Nagarajan, M Renuga, A Manikandan, S Dhanasekaran Journal of Circuits, Systems and Computers 33 (01), 2450003, 2024 | 2 | 2024 |
| Design of SB-GNRFET and D-GNRFET using QuantumATK P Venkatramana, P Nagarajan, SJ Basha 2023 International Conference on Networking and Communications (ICNWC), 1-4, 2023 | 2 | 2023 |
| Investigating Wireless Optical Communication Systems for inter satellite communication using QPSK Modulation Technique T Kavitha, P Nagarajan, R Ganesamoorthy, A Arulmary, S Jana Data Intelligence and Cognitive Informatics: Proceedings of ICDICI 2021, 849-856, 2022 | 2 | 2022 |
Ashokkumar.NProfessorVerified email at vidyanikethan.edu
