| Low power finite state machine synthesis using power-gating S Nath Pradhan, M Tilak Kumar, S Chattopadhyay Integration, the VLSI Journal, 2011 | 32* | 2011 |
| Implementation of circuit in different adiabatic logic A Chaudhuri, M Saha, M Bhowmik, SN Pradhan, S Das 2015 2nd International Conference on Electronics and Communication Systems …, 2015 | 27 | 2015 |
| IoT based design of air quality monitoring system web server for android platform KD Purkayastha, RK Mishra, A Shil, SN Pradhan Wireless Personal Communications 118 (4), 2921-2940, 2021 | 23 | 2021 |
| An approach for low power design of power gated finite state machines considering partitioning and state encoding together P Choudhury, SN Pradhan Journal of Low Power Electronics 8 (4), 452-463, 2012 | 22 | 2012 |
| Two-level AND-XOR networks synthesis with area-power trade-off SN Pradhan, S Chattopadhyay International Journal of Computer Science and Network Security 8 (9), 365-375, 2008 | 20 | 2008 |
| Reduction of noise using continuously changing variable clock and clock gating for IC chips S Bhowmik, D Deb, SN Pradhan, BK Bhattacharyya IEEE Transactions on Components, Packaging and Manufacturing Technology 6 (6 …, 2016 | 19 | 2016 |
| Thermal aware FPRM based AND-XOR network synthesis of logic circuits A Das, SN Pradhan 2015 IEEE 2nd International Conference on Recent Trends in Information …, 2015 | 14 | 2015 |
| Integrated power-gating and state assignment for low power FSM synthesis SN Pradhan, MT Kumar, S Chattopadhyay 2008 IEEE Computer Society Annual Symposium on VLSI, 269-274, 2008 | 14 | 2008 |
| Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. A Das, SN Pradhan VLSI Design, 2016 | 13 | 2016 |
| An elitist area-power density trade-off in VLSI floorplan using genetic algorithm A Das, SR Choudhury, BK Kumar, SN Pradhan 2012 7th International Conference on Electrical and Computer Engineering …, 2012 | 12 | 2012 |
| NBTI-aware power gating design with dynamically varying stress probability control on sleep transistor A Bhattacharjee, SN Pradhan Journal of Circuits, Systems and Computers 30 (11), 2120004, 2021 | 11 | 2021 |
| Area-power-temperature aware AND-XOR network synthesis based on shared mixed polarity reed-muller expansion A Das, SN Pradhan International Journal of Intelligent Systems and Applications 10 (12), 35, 2018 | 11 | 2018 |
| Facial expression recognition based on eigenspaces and principle component analysis A Saha, SN Pradhan International Journal of Computational Vision and Robotics 8 (2), 190-200, 2018 | 11 | 2018 |
| Leakage reduction of SRAM-based look-up table using dynamic power gating A Nag, D Nath, SN Pradhan Journal of Circuits, Systems and Computers 26 (03), 1750041, 2017 | 11 | 2017 |
| NSGA-II based thermal-aware mixed polarity dual Reed–Muller network synthesis using parallel tabular technique A Das, YC Hareesh, SN Pradhan Journal of Circuits, Systems and Computers 29 (15), 2020008, 2020 | 9 | 2020 |
| Design time temperature reduction in mixed polarity dual Reed-Muller network: a NSGA-II based approach A Das, SN Pradhan Advances in Electrical and Computer Engineering 20 (1), 99-104, 2020 | 9 | 2020 |
| Clock jitter reduction and flat frequency generation in PLL using autogenerated control feedback S Bhowmik, SN Pradhan, BK Bhattacharyya IEEE Transactions on Components, Packaging and Manufacturing Technology 7 …, 2017 | 9 | 2017 |
| Area, power and temperature optimization during binary decision diagram based circuit synthesis A Das, A Debnath, SN Pradhan 2017 Devices for Integrated Circuit (DevIC), 778-782, 2017 | 9 | 2017 |
| Low power and high testable Finite State Machine synthesis SN Pradhan, P Choudhury 2015 International Conference and Workshop on Computing and Communication …, 2015 | 9 | 2015 |
| Thermal aware output polarity selection of programmable logic arrays A Das, SN Pradhan 2015 International Conference on Electronic Design, Computer Networks …, 2015 | 9 | 2015 |
