| High-performance hardware merge sorter S Mashimo, T Van Chu, K Kise 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 59 | 2017 |
| A high-performance and cost-effective hardware merge sorter without feedback datapath M Saitoh, EA Elsayed, T Van Chu, S Mashimo, K Kise 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 36 | 2018 |
| Ultra-fast NoC emulation on a single FPGA T Van Chu, S Sato, K Kise 2015 25th International Conference on Field Programmable Logic and …, 2015 | 32 | 2015 |
| Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga TV Chu, S Sato, K Kise ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (4), 1-27, 2017 | 23 | 2017 |
| Hiddenite: 4K-PE hidden network inference 4D-tensor engine exploiting on-chip model construction achieving 34.8-to-16.0 TOPS/W for CIFAR-100 and ImageNet K Hirose, J Yu, K Ando, Y Okoshi, ÁL García-Arias, J Suzuki, T Van Chu, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 20 | 2022 |
| The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs M Imai, T Van Chu, K Kise, T Yoneda 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016 | 20 | 2016 |
| A cost-effective and scalable merge sorter tree on FPGAs T Usui, T Van Chu, K Kise 2016 Fourth International Symposium on Computing and Networking (CANDAR), 47-56, 2016 | 19 | 2016 |
| Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension K Kawamura, J Yu, D Okonogi, S Jimbo, G Inoue, A Hyodo, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 42-44, 2023 | 15 | 2023 |
| Cost-effective and high-throughput merge network: Architecture for the fastest FPGA sorting accelerator S Mashimo, T Van Chu, K Kise ACM SIGARCH Computer Architecture News 44 (4), 8-13, 2017 | 7 | 2017 |
| Ultrasmall: The smallest MIPS soft processor H Nakatsuka, Y Tanaka, T Van Chu, S Takamaeda-Yamazaki, K Kise 2014 24th International Conference on Field Programmable Logic and …, 2014 | 7 | 2014 |
| An exploration of state-of-the-art automation frameworks for FPGA-based DNN acceleration F Hamanaka, T Odan, K Kise, T Van Chu IEEE Access 11, 5701-5713, 2023 | 6 | 2023 |
| Multicoated Supermasks Enhance Hidden Networks. Y Okoshi, ÁL García-Arias, K Hirose, K Ando, K Kawamura, T Van Chu, ... ICML, 17045-17055, 2022 | 6 | 2022 |
| A high-performance and flexible fpga inference accelerator for decision forests based on prior feature space partitioning T Van Chu, R Kitajima, K Kawamura, J Yu, M Motomura 2021 International Conference on Field-Programmable Technology (ICFPT), 1-10, 2021 | 4 | 2021 |
| LEF: An effective routing algorithm for two-dimensional meshes T Van Chu, K Kise IEICE TRANSACTIONS on Information and Systems 102 (10), 1925-1941, 2019 | 4 | 2019 |
| Enabling fast and accurate emulation of large-scale network on chip architectures on a single FPGA T Van Chu, S Sato, K Kise 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 4 | 2015 |
| KNoCEmu: High speed FPGA emulator for kilo-node scale NoCs T Van Chu, S Sato, K Kise 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs …, 2014 | 4 | 2014 |
| Dependency-driven trace-based Network-on-Chip emulation on FPGAs TV Chu, K Kise, K Tanaka Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020 | 3 | 2020 |
| A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers S Jimbo, D Okonogi, K Ando, T Van Chu, J Yu, M Motomura, K Kawamura IEICE TRANSACTIONS on Information and Systems 105 (12), 2019-2031, 2022 | 2 | 2022 |
| Edge inference engine for deep & random sparse neural networks with 4-bit Cartesian-product MAC array and pipelined activation aligner K Ando, J Yu, K Hirose, H Nakahara, K Kawamura, T Van Chu, ... 2021 IEEE Hot Chips 33 Symposium (HCS), 1-21, 2021 | 2 | 2021 |
| ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation J Suzuki, K Ando, K Hirose, K Kawamura, T Van Chu, M Motomura, J Yu 2020 Eighth International Symposium on Computing and Networking (CANDAR …, 2020 | 2 | 2020 |
