‪Santosh Kumar Padhi‬ - ‪Google Scholar‬

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Citations	7	7
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Co-authors

Vadthiya NarendarNational Institute of Technology WarangalVerified email at nitw.ac.in
Atul Kumar NishadAssistant Professor, National Institute of Technology Warangal, INDIAVerified email at nitw.ac.in

Santosh Kumar Padhi

Santosh Kumar Padhi

Verified email at student.nitw.ac.in

Semiconductor Devices and Circuits Negative Capacitance


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
On the design of p-channel step-FinFET at sub-10nm node: a parametric analysis SK Padhi, V Narendar, AK Nishad Microelectronics Journal 126, 105505, 2022	5	2022
A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation R Andavarapu, S Bagati, S Valasa, VR Kotha, S Bhukya, SK Padhi, ... IEEE Transactions on Electron Devices, 2023	2	2023
A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis SK Padhi, V Narendar, AK Nishad Microelectronics Journal, 106139, 2024		2024

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